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ORCID10th FPL 2000: Villach, Austria
- Reiner W. Hartenstein, Herbert Grünbacher:
Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings. Lecture Notes in Computer Science 1896, Springer 2000, ISBN 3-540-67899-9
Invited Keynotes
- Tsugio Makimoto:
The Rising Wave of Field Programmability. 1-6 - Sriram Govindarajan, Ranga Vemuri
:
Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS. 7-18
Network Processors
- Johan Ditmar, Kjell Torkelsson, Axel Jantsch:
A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization. 19-28 - Xinan Tang, Manning Aalsma, Raymond Jou:
A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors. 29-38 - Marios Iliopoulos, Theodore Antonakopoulos:
Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits. 39-47 - Hamish Fallside, Michael John Sebastian Smith:
Internet Connected FPL. 48-57
Prototyping
- Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
Field Programmable Communication Emulation and Optimization for Embedded System Design. 58-67 - Helena Krupnova, Gabriele Saucier:
FPGA-Based Emulation: Industrial and Custom Prototyping Solutions. 68-77 - Rainer Kress, Andreas Pyttel, Alexander Sedlmeier:
FPGA-Based Prototyping for Product Definition. 78-86 - E. Cantó, Juan Manuel Moreno, Joan Cabestany, Ignacio Lacadena, Josep Maria Insenser:
Implementation of Virtual Circuits by Means of the FIPSOC Devices. 87-95
Dynamically Reconfigurable 1
- Jörn Gause, Peter Y. K. Cheung, Wayne Luk:
Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT. 96-105 - Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro Mei, Viktor K. Prasanna:
A Self-Reconfigurable Gate Array Architecture. 106-120 - Harald Simmler, L. Levinson, Reinhard Männer:
Multitasking on FPGA Coprocessors. 121-130 - Milan Vasilko:
Design Visualisation for Dynamically Reconfigurable Systems. 131-140 - David Robinson, Patrick Lysaght:
Verification of Dynamically Reconfigurable Logic. 141-150
Miscellaneous 1
- Thomas Bartzick, Michael Henze, Jens Kickler, Kai Woska:
Design of a Fault Tolerant FPGA. 151-156 - Rob McCready:
Real-Time Face Detection on a Configurable Hardware System. 157-162 - Petr Pfeifer:
Multifunctional Programmable Single-Board CAN Monitoring Module. 163-168 - Pawel Tomaszewicz:
Self-Testing of Linear Segments in User-Programmed FPGAs. 169-174 - G. Lías, María Dolores Valdés, Miguel A. Domínguez, María José Moure:
Implementing a Fieldbus Interface Using an FPGA. 175-180
Technology Mapping and Routing & Placement
- Srini Krishnamoorthy, Sriram Swaminathan, Russell Tessier:
Area-Optimized Technology Mapping for Hybrid FPGAs. 181-190 - Joerg Abke, Erich Barke:
CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs. 191-200 - Sushil Chandra Jain, Anshul Kumar, Shashi Kumar:
Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards. 201-210 - Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman:
A Placement Algorithm for FPGA Designs with Multiple I/O Standards. 211-220 - Holger Kropp, Carsten Reuter:
A Mapping Methodology for Code Trees onto LUT-Based FPGAs. 221-229
Biologically Inspired Methods
- Jim Tørresen:
Possibilities and Limitations of Applying Evolvable Hardware to Real-World Applications. 230-239 - Yoshiki Yamaguchi, Akira Miyashita, Tsutomu Maruyama, Tsutomu Hoshino:
A Co-processor System with a Virtex FPGA for Evolutionary Computation. 240-249 - Christine Bauer, Peter Zipf, Hans Wojtkowiak:
System Design with Genetic Algorithms. 250-259 - Jihan Zhu, George J. Milne:
Implementing Kak Neural Networks on a Reconfigurable Computing Platform. 260-269 - Selene Maya, M. Rocio Reynoso, César Torres-Huitzil, Miguel O. Arias-Estrada:
Compact Spiking Neural Network Implementation in FPGA. 270-276
Invited Keynote
- Jan M. Rabaey:
Silicon Platforms for the Next Generation Wireless Systems - What Role Does Reconfigurable Hardware Play? 277-285
Invited Papers
- John S. McCaskill, Patrick Wagler:
From Reconfigurability to Evolution in Construction Systems: Spanning the Electronic, Microfluidic and Biomolecular Domains. 286-299 - Michel Renovell:
A Specific Test Methodology for Symmetric SRAM-Based FPGAs. 300-311
Mobile Communication
- Jürgen Becker, Thilo Pionteck, Manfred Glesner:
DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications. 312-321 - Alfred Blaickner, O. Nagy, Herbert Grünbacher:
Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic. 322-331 - Xavier Revés, Antoni Gelonch, Ferran Casadevall, José L. García:
Software Radio Reconfigurable Hardware System (SHaRe). 332-341 - Javier Ramírez, Antonio García, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-Ruíz:
Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform. 342-351
Dynamically Reconfigurable 2
- Scott McMillan, Steve Guccione:
Partial Run-Time Reconfiguration Using JRTR. 352-360 - Xue-Jie Zhang, Kam-Wing Ng, Wayne Luk:
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems. 361-370 - Tero Rissa, Jarkko Niittylahti:
A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs. 371-378 - Hossam A. ElGindy, Martin Middendorf, Hartmut Schmeck, Bernd Schmidt:
Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer. 379-388
Design Space Exploration
- Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures. 389-399 - Paul M. Heysters, Jaap Smit, Gerard J. M. Smit, Paul J. M. Havinga:
Mapping of DSP Algorithms on Field Programmable Function Arrays. 400-411 - Darko Stefanovic, Margaret Martonosi:
On Availability of Bit-Narrow Operations in General-Purpose Applications. 412-421 - Radhika S. Grover, Weijia Shang, Qiang Li:
A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers. 422-431 - Frank Wolz, Reiner Kolla:
A New Floorplanning Method for FPGA Architectural Research. 432-442
Miscellaneous 2
- Sameer Wadhwa, Andreas Dandalis:
Efficient Self-Reconfigurable Implementations Using On-chip Memory. 443-448 - Alexander Glasmacher, Kai Woska:
Design and Implementation of an XC6216 FPGA Model in Verilog. 449-455 - Jernej Andrejas, Andrej Trost:
Reusable DSP Functions in FPGAs. 456-461 - Mark Redekopp, Andreas Dandalis:
A Parallel Pipelined SAT Solver for FPGAs. 462-468 - Abdellah Touhafi:
A Multi-node Dynamic Reconfigurable Computing System with Distributed Reconfiguration Controller. 469-474
Applications 1
- Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano:
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. 475-484 - Stephen J. Bellis, William P. Marnane:
A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System. 485-494 - Stephen J. Melnikoff, Philip James-Roxby, Steven F. Quigley, Martin J. Russell:
Reconfigurable Computing for Speech Recognition: Preliminary Findings. 495-504 - Hagen Ploog, Mathias Schmalisch, Dirk Timmermann:
Security Upgrade of Existing ISDN Devices by Using Reconfigurable Logic. 505-514 - Takahiro Miomo, Koichi Yasuoka, Masanori Kanazawa:
The Fastest Multiplier on FPGAs with Redundant Binary Representation. 515-524
Optimization
- Rolf Enzler, Tobias Jeger, Didier Cottet, Gerhard Tröster:
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs. 525-534 - Russell Tessier, Heather Giza:
Balancing Logic Utilization and Area Efficiency in FPGAs. 535-544 - John Marty Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici:
Performance Penalty for Fault Tolerance in Roving STARs. 545-554 - Jian Qiao, Makoto Ikeda, Kunihiro Asada:
Optimum Functional Decomposition for LUT-Based FPGA Synthesis. 555-564 - Michael Eisenring, Marco Platzner:
Optimization of Run-Time Reconfigurable Embedded Systems. 565-574
Invited Keynote
- Tom Kean:
It's FPL, Jim - But Not as We Know It! Opportunities for the New Commercial Architectures. 575-584
Invited Papers
- Hideharu Amano, Yuichiro Shibata, Masaki Uno:
Reconfigurable Systems: New Activities in Asia. 585-594 - Oskar Mencer, Heiko Hübert, Martin Morf, Michael J. Flynn:
StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox. 595-604
Architectures
- Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon:
Stream Computations Organized for Reconfigurable Execution (SCORE). 605-614 - Holger Lange, Andreas Koch:
Memory Access Schemes for Configurable Processors. 615-625 - Andreas C. Döring, Gunther Lustig:
Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory. 626-635 - Arran Derbyshire, Wayne Luk:
Combining Serialisation and Reconfiguration for FPGA Designs. 636-645
Methodology and Technology
- George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Multiple-Wordlength Resource Binding. 646-655 - Milan Vasilko, Graham Benyon-Tinker:
Automatic Temporal Floorplanning with Guaranteed Solution Feasibility. 656-664 - Kazuo Aoyama, Hiroshi Sawada, Akira Nagoya, Kazuo Nakajima:
A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology. 665-674 - Andrzej Krasniewski:
Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs. 675-684
Compilation and Related Issues
- Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hideharu Amano:
Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware. 685-694 - Bernardo Kastrup, Jeroen Trum, Orlando Moreira, Jan Hoogerbrugge, Jef L. van Meerbergen:
Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis. 695-706 - Oliver Diessel, George J. Milne:
Behavioural Language Compilation with Virtual Hardware Management. 707-717 - Valery Sklyarov:
Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs. 718-728
Applications 2
- Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn, Kouji Konishi:
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem. 729-738 - Martyn Edwards, Peter Green:
The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware. 739-748 - Tim Courtney, Richard H. Turner, Roger F. Woods:
Multiplexer Based Reconfiguration for Virtex Multipliers. 749-758 - Christophe Bobda, Thomas Lehmann:
Efficient Building of Word Recongnizer in FPGAs for Term-Document Matrices Construction. 759-768
Short Papers
- Christian Siemers:
Reconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-Scheduling. 769-772 - Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidzadeh:
FPGA Implementation of a Prototype WDM On-Line Scheduler. 773-776 - Jens Hildebrandt, Dirk Timmermann:
An FPFA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard-Time Systems. 777-780 - Sergej Sawitzki, Jens Schönherr, Rainer G. Spallek, Bernd Straube:
Formal Verification of a Reconfigurable Microprocessor. 781-784 - Rafael Gadea Gironés, Vicente Herrero-Bosch, Angel Sebastiá, Antonio Mocholí Salcedo:
The Role of the Embedded Memories in the Implementation of Artificial Neural Networks. 785-788 - Guy Lecurieux Lafayette:
Programmable System Level Integration Brings System-on-Chip Design to the Desktop. 789-792 - A. Hilton, J. Hall:
On Applying Software Development Best Practice to FPFAs in Safety Critical Systems. 793-796 - Brandon Blodget:
Pre-route Assistant: A Routing Tool for Run-Time Reconfiguration. 797-800 - Tomoyoshi Kobori, Tsutomu Maruyama, Tsutomu Hoshino:
High Speed Computation of Lattice gas Automata with FPFA. 801-804 - Tsunemichi Shiozawa, Norbert Imlig, Kouichi Nagami, Kiyoshi Oguri, Akira Nagoya, Hiroshi Nakada:
An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture. 805-809 - Bogdan Matasaru, Tudor Jebelean:
FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers. 810-813 - Lukás Sekanina, Azeddien M. Sllame:
Toward Uniform Approach to Design of Evolvable Hardware Based Systems. 814-817 - Andrej Trost, Andrej Zemva, Baldomir Zajc:
Educational Programmable Hardware Prototyping and Verification System. 818-821 - Rolf Hoffmann, Bernd Ulmann, Klaus-Peter Völkmann, Stefan Waldschmidt:
A Stream Processor Architecture Based on the Configurable CEPRA-S. 822-825 - Uwe Hatnik, Jürgen Haufe, Peter Schwarz:
An Innovative Approach to Couple EDA Tools with Reconfigurable Hardware. 826-829 - Kalle Tammemäe, T. Evartson:
FPL Curriculum at Tallinn Technical University. 830-833 - Jean-Michel Raczinski, Stéphane Sladek:
The Modular Architecture of SYNTHUP, FPFA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing. 834-837 - André Brinkmann, Dominik Langen, Ulrich Rückert:
A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor. 838-841 - Juanjo Noguera, Rosa M. Badia:
Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers. 842-845 - Chris Phillips:
Wireless Base Station Design Using a Reconfigurable Communications Processor. 846-848 - Erwan Fabiani, Dominique Lavenier:
Placement of Linear Arrays. 849-852
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