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ORCIDACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 14
Volume 14, Number 1, January 2009
- Joachim Keinert, Martin Streubühr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt
, Jürgen Teich, Michael Meredith:
SystemCoDesigner - an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications. 1:1-1:23 - Andreas Hansson, Kees Goossens, Marco Bekooij, Jos Huisken:
CoMPSoC: A template for composable and predictable multi-processor system on chips. 2:1-2:24 - Stefan Valentin Gheorghita, Martin Palkovic, Juan Hamers, Arnout Vandecappelle, Stelios Mamagkakis, Twan Basten, Lieven Eeckhout, Henk Corporaal, Francky Catthoor, Frederik Vandeputte, Koen De Bosschere:
System-scenario-based design of dynamic embedded systems. 3:1-3:45 - Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty:
SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects. 4:1-4:27 - Zhong-Yi Jin, Curt Schurgers, Rajesh K. Gupta:
A gateway node with duty-cycled radio and processing subsystems for wireless sensor networks. 5:1-5:17 - Chin-Hsien Wu:
An energy-efficient I/O request mechanism for multi-bank flash-memory storage systems. 6:1-6:25 - Swapna R. Dontharaju, Shen Chih Tung, James T. Cain, Leonid Mats, Marlin H. Mickle, Alex K. Jones:
A design automation and power estimation flow for RFID systems. 7:1-7:31 - Ali Dasdan:
Provably efficient algorithms for resolving temporal and spatial difference constraint violations. 8:1-8:24 - Arnab Sinha, Pallab Dasgupta, Bhaskar Pal, Sayantan Das, Prasenjit Basu, P. P. Chakrabarti:
Design intent coverage revisited. 9:1-9:32 - Zijiang Yang, Chao Wang, Aarti Gupta, Franjo Ivancic:
Model checking sequential software programs via mixed symbolic analysis. 10:1-10:26 - Gayatri Mehta, Justin Stander, Mustafa Baz, Brady Hunsaker, Alex K. Jones:
Interconnect customization for a hardware fabric. 11:1-11:32 - Chiu-Wing Sham, Evangeline F. Y. Young, Jingwei Lu:
Congestion prediction in early stages of physical design. 12:1-12:18 - Yi Zhu, Yuanfang Hu, Michael B. Taylor, Chung-Kuan Cheng:
Energy and switch area optimizations for FPGA global routing architectures. 13:1-13:25 - Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh:
Opposite-phase register switching for peak current minimization. 14:1-14:29 - Yen-Chun Lin, Li-Ling Hung:
Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2. 15:1-15:13 - Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang:
Lens aberration aware placement for timing yield. 16:1-16:26 - Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng:
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications. 17:1-17:17 - Pedro Reviriego, Juan Antonio Maestro:
Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS. 18:1-18:10
Volume 14, Number 2, March 2009
- Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran:
Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis. 19:1-19:41 - Sudeep Pasricha, Young-Hwan Park, Nikil D. Dutt, Fadi J. Kurdahi:
System-level PVT variation-aware power exploration of on-chip communication architectures. 20:1-20:25 - Rajdeep Mukhopadhyay, Subrat Kumar Panda, Pallab Dasgupta, John Gough:
Instrumenting AMS assertion verification on commercial platforms. 21:1-21:47 - Martin Palkovic, Francky Catthoor, Henk Corporaal:
Trade-offs in loop transformations. 22:1-22:30 - Franco Fummi, Mirko Loghi, Massimo Poncino, Graziano Pravadelli:
A cosimulation methodology for HW/SW validation and performance estimation. 23:1-23:32 - Hiroaki Inoue, Tsuyoshi Abe, Kazuhisa Ishizaka, Junji Sakai, Masato Edahiro:
Dynamic security domain scaling on embedded symmetric multiprocessors. 24:1-24:23 - Meikang Qiu, Edwin Hsing-Mean Sha:
Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems. 25:1-25:30 - Xiangrong Zhou, Chenjie Yu, Peter Petrov:
Temperature-aware register reallocation for register file power-density minimization. 26:1-26:22 - Yu-Ru Hong, Juinn-Dar Huang:
Reducing fault dictionary size for million-gate large circuits. 27:1-27:14 - Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
Efficient partial scan cell gating for low-power scan-based testing. 28:1-28:15 - Daler N. Rakhmatov:
Battery voltage modeling for portable systems. 29:1-29:36 - Yokesh Kumar, Prosenjit Gupta:
External memory layout vs. schematic. 30:1-30:20 - Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang:
Skew-aware polarity assignment in clock tree. 31:1-31:17 - Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan:
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability. 32:1-32:21 - Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas:
FPGA-based hardware acceleration for Boolean satisfiability. 33:1-33:11
Volume 14, Number 3, May 2009
- Avinash Malik, Zoran A. Salcic, Partha S. Roop:
SystemJ compilation using the tandem virtual machine approach. 34:1-34:37 - Jason Cong, Yiping Fan, Junjuan Xu:
Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture. 35:1-35:31 - Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor:
Playing the trade-off game: Architecture exploration using Coffeee. 36:1-36:37 - Dipankar Das, P. P. Chakrabarti, Rajeev Kumar:
Scenario-based timing verification of multiprocessor embedded applications. 37:1-37:58 - Philippe Grosse, Yves Durand, Paul Feautrier:
Methods for power optimization in SOC-based data flow systems. 38:1-38:20 - Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung:
Word-length selection for power minimization via nonlinear optimization. 39:1-39:28 - Pedro Marques Morgado, Paulo F. Flores, L. Miguel Silveira:
Generating realistic stimuli for accurate power grid analysis. 40:1-40:26 - Hao Yu, Joanna Ho, Lei He:
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. 41:1-41:31 - Bo Liu, Francisco V. Fernández, Georges G. E. Gielen, Rafael Castro-López, Elisenda Roca:
A memetic approach to the automatic design of high-performance analog integrated circuits. 42:1-42:24 - Madhu Mutyam:
Selective shielding technique to eliminate crosstalk transitions. 43:1-43:20 - Baris Taskin, Joseph Demaio, Owen Farell, Michael Hazeltine, Ryan Ketner:
Custom topology rotary clock router with tree subnetworks. 44:1-44:14 - Chih-Hung Liu, Shih-Yi Yuan, Sy-Yen Kuo, Szu-Chi Wang:
High-performance obstacle-avoiding rectilinear steiner tree construction. 45:1-45:29 - Tan Yan, Martin D. F. Wong:
Theories and algorithms on single-detour routing for untangling twisted bus. 46:1-46:21
Volume 14, Number 4, August 2009
- Sivaram Gopalakrishnan, Priyank Kalla:
2009 ACM TODAES best paper award: Optimization of polynomial datapaths using finite ring algebra. 47:1 - Peter Bertels, Wim Heirman, Erik H. D'Hollander, Dirk Stroobandt:
Efficient memory management for hardware accelerated Java Virtual Machines. 48:1-48:18 - Miad Faezipour, Mehrdad Nourani, Rina Panigrahy:
A hardware platform for efficient worm outbreak detection. 49:1-49:29 - Byunghyun Lee, Ki-Seok Chung, Bontae Koo, Nak-Woong Eum, Taewhan Kim:
Thermal sensor allocation and placement for reconfigurable systems. 50:1-50:23 - Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
T-trees: A tree-based representation for temporal and three-dimensional floorplanning. 51:1-51:28 - Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin:
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs. 52:1-52:26 - Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma:
Leakage reduction, delay compensation using partition-based tunable body-biasing techniques. 53:1-53:22 - Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam:
Variation-aware multimetric optimization during gate sizing. 54:1-54:30 - Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Power-delay optimization in VLSI microprocessors by wire spacing. 55:1-55:28 - Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian:
SUPERB: Simulator utilizing parallel evaluation of resistive bridges. 56:1-56:21
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