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2010 – 2019
- 2017
[c20]Hugh Mair, Ericbill Wang, Alice Wang, Ping Kao, Yuwen Tsai, Sumanth Gururajarao, Rolf Lagerquist, Jin Son, Gordon Gammie, Gordon Lin, Achuta Thippana, Kent Li, Manzur Rahman, Wuan Kuo, David Yen, Yi-Chang Zhuang, Ue Fu, Hung-Wei Wang, Mark Peng, Cheng-Yuh Wu, Taner Dosluoglu
, Anatoly Gelman, Daniel Dia, Girishankar Gurumurthy, Tony Hsieh, W. X. Lin, Ray Tzeng, Jengding Wu, C. H. Wang, Uming Ko:
3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance. ISSCC 2017: 56-57- 2016
- [c19]Gilad Yahalom, Stacy Ho, Alice Wang, Uming Ko, Anantha P. Chandrakasan:
Analog-digital partitioning and coupling in 3D-IC for RF applications. 3DIC 2016: 1-4 - [c18]Sunghyun Park, Alice Wang, Uming Ko, Li-Shiuan Peh, Anantha P. Chandrakasan:
Enabling simultaneously bi-directional TSV signaling for energy and area efficient 3D-ICs. DATE 2016: 163-168 - [c17]Hugh Mair, Gordon Gammie, Alice Wang, Rolf Lagerquist, C. J. Chung, Sumanth Gururajarao, Ping Kao, Anand Rajagopalan, Anirban Saha, Amit Jain, Ericbill Wang, Shichin Ouyang, Huajun Wen, Achuta Thippana, HsinChen Chen, Syed Rahman, Minh Chau, Anshul Varma, Brian Flachs, Mark Peng, Alfred Tsai, Vincent Lin, Ue Fu, Wuan Kuo, Lee-Kee Yong, Clavin Peng, Leo Shieh, Jengding Wu, Uming Ko:
4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance. ISSCC 2016: 76-77 - 2015
- [c16]Hugh Mair, Gordon Gammie, Alice Wang, Sumanth Gururajarao, Ichiro Lin, HsinChen Chen, Wuan Kuo, Anand Rajagopalan, Wei-Zheng Ge, Rolf Lagerquist, Syed Rahman, C. J. Chung, Simon Wang, Lee-Kee Wong, Yi-Chang Zhuang, Kent Li, Jidong Wang, Minh Chau, Yijing Liu, Daniel Dia, Mark Peng, Uming Ko:
23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques. ISSCC 2015: 1-3 - 2014
- [c15]Alice Wang, Tsung-Yao Lin, Shichin Ouyang, Wei-Hung Huang, Jidong Wang, Shu-Hsin Chang, Sheng-Ping Chen, Chun-Hsiung Hu, J. C. Tai, Koan-Sin Tan, Meng-Nan Tsou, Ming-Hsien Lee, Gordon Gammie, Chi-Wei Yang, Chih-Chieh Yang, Yeh-Chi Chou, Shih-Hung Lin, Wuan Kuo, Chi-Jui Chung, Lee-Kee Yong, Chia-Wei Wang, Kin Hooi Dia, Cheng-Hsing Chien, You-Ming Tsao, N. K. Singh, Rolf Lagerquist, Chih-Cheng Chen, Uming Ko:
10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor. ISSCC 2014: 180-181 - 2013
- [j7]Maurits Ortmanns, Timothy C. Fischer, Uming Ko, Wim Dehaene, Yasuhiro Takai:
Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 48(1): 3-7 (2013) - [c14]Shekhar Borkar, Uming Ko, Ali Keshavarzi, Eugenio Cantatore:
EP3: Empowering the killer SoC applications of 2020. ISSCC 2013: 517 - 2012
- [j6]Nathan Ickes, Gordon Gammie, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko:
A 28 nm 0.6 V Low Power DSP for Mobile Applications. IEEE J. Solid State Circuits 47(1): 35-46 (2012) - [c13]Uming Ko:
Ultra-low power challenges for the next generation ASIC. ISLPED 2012: 365-366 - 2011
- [c12]Gordon Gammie, Nathan Ickes, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko:
A 28nm 0.6V low-power DSP for mobile applications. ISSCC 2011: 132-134 - 2010
- [j5]Gordon Gammie, Alice Wang, Hugh Mair, Rolf Lagerquist, Minh Chau, Philippe Royannez, Sumanth Gururajarao, Uming Ko:
SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors. Proc. IEEE 98(2): 144-159 (2010)
2000 – 2009
- 2008
- [c11]Gordon Gammie, Alice Wang, Minh Chau, Sumanth Gururajarao, Robert Pitts, Fabien Jumel, Stacey Engel, Philippe Royannez, Rolf Lagerquist, Hugh Mair, Jeff Vaccani, Greg Baldwin, Keerthi Heragu, Rituparna Mandal, Michael Clinton, Don Arden, Uming Ko:
A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques. ISSCC 2008: 258-259 - 2007
- [c10]Philippe Royannez, Hugh Mair, Michael Clinton, Uming Ko:
Solutions for logic and processor core design at the 45nm technology node & and below. ICECS 2007: 923-926 - 2006
- [c9]Andrew Yang, Rajit Chandra, Simon Burke, Javier A. DeLaCruz, Sribalan Santhanam, Uming Ko:
Entering the hot zone - can you handle the heat and be cool? DAC 2006: 174-175 - 2005
- [c8]Philippe Royannez, Hugh Mair, Franck Dahan, Mike Wagner, Mark Streeter, Laurent Bouetel, Joel Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, Claudine Raibaut, Uming Ko:
A design platform for 90-nm leakage reduction techniques. DAC 2005: 549-550 - 2000
- [j4]Uming Ko, Poras T. Balsara:
High-performance energy-efficient D-flip-flop circuits. IEEE Trans. Very Large Scale Integr. Syst. 8(1): 94-98 (2000)
1990 – 1999
- 1999
- [c7]Uming Ko, Mike McMahan, Edgar Auslander:
DSP for the Third Generation Wireless Communications. ICCD 1999: 516-520 - 1998
- [j3]Uming Ko, Poras T. Balsara, Ashwini K. Nanda:
Energy optimization of multilevel cache architectures for RISC and CISC processors. IEEE Trans. Very Large Scale Integr. Syst. 6(2): 299-308 (1998) - 1997
- [c6]David Li, Andrew Pua, Pranjal Srivastava, Uming Ko:
A Repeater Optimization Methodology for Deep Sub-Micron, High Performance Processors. ICCD 1997: 726-731 - [c5]June Jiang, Kan Lu, Uming Ko:
High-performance, low-power design techniques for dynamic to static logic interface. ISLPED 1997: 12-17 - [c4]Uming Ko, Andrew Pua, Anthony M. Hill, Pranjal Srivastava:
Hybrid dual-threshold design techniques for high-performance processors with low-power features. ISLPED 1997: 307-311 - 1996
- [c3]Uming Ko, Anthony M. Hill, Poras T. Balsara:
Design techniques for high performance, energy efficient control logic. ISLPED 1996: 97-100 - 1995
- [j2]Uming Ko, T. Balsara, Wai Lee:
Low-power design techniques for high-performance CMOS adders. IEEE Trans. Very Large Scale Integr. Syst. 3(2): 327-333 (1995) - [j1]Uming Ko, Poras T. Balsara:
Short-circuit power driven gate sizing technique for reducing power dissipation. IEEE Trans. Very Large Scale Integr. Syst. 3(3): 450-455 (1995) - [c2]Uming Ko, Poras T. Balsara, Ashwini K. Nanda:
Energy optimization of multi-level processor cache architectures. ISLPD 1995: 45-49
1980 – 1989
- 1985
- [c1]Uming Ko, Dinesh G. Patel, Francois J. Henley:
Contactless VLSI Laser Probing. ITC 1985: 930-937
Coauthor Index
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