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ORCIDAbhishek Kumar Jain
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2020 – today
- 2023
[c12]Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, Dinesh Gaitonde:
Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs. FCCM 2023: 133-143- [i3]Paolo D'Alberto, Abhishek Kumar Jain, Ismail Bustany, Henri Fraisse, Mansimran Benipal:
Entropy Maximization in Sparse Matrix by Vector Multiplication (maxESpMV). CoRR abs/2308.00106 (2023) - 2022
- [j4]Abhishek Kumar Jain
, Douglas L. Maskell, Suhaib A. Fahmy:
Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation. IEEE Trans. Parallel Distributed Syst. 33(6): 1478-1490 (2022) - 2021
- [c11]Abhishek Kumar Jain, Sharan Kumar, Aashish Tripathi, Dinesh Gaitonde:
Sparse Deep Neural Network Acceleration on HBM-Enabled FPGA Platform. HPEC 2021: 1-7 - 2020
- [c10]Abhishek Kumar Jain, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde:
A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs. FPL 2020: 127-132 - [c9]Xiangwei Li, Kizheppatt Vipin, Douglas L. Maskell, Suhaib A. Fahmy, Abhishek Kumar Jain:
High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay. ISCAS 2020: 1-5 - [c8]Abhishek Kumar Jain:
Role of on-chip networks in building domain-specific architectures (DSAs) for sparse computations (invited). SLIP 2020: 9
2010 – 2019
- 2019
- [j3]Abhishek Kumar Jain, G. Scott Lloyd, Maya B. Gokhale:
Performance Assessment of Emerging Memories Through FPGA Emulation. IEEE Micro 39(1): 8-16 (2019) - 2018
- [c7]Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy:
A time-multiplexed FPGA overlay with linear interconnect. DATE 2018: 1075-1080 - [c6]Abhishek Kumar Jain, G. Scott Lloyd, Maya B. Gokhale:
Microscope on Memory: MPSoC-Enabled Computer Memory System Assessments. FCCM 2018: 173-180 - 2017
- [b1]Abhishek Kumar Jain:
Architecture centric coarse-grained FPGA overlays. Nanyang Technological University, Singapore, 2017 - [i2]Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy:
Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays. CoRR abs/1705.02730 (2017) - 2016
- [c5]Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy:
Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs? DASC/PiCom/DataCom/CyberSciTech 2016: 586-593 - [c4]Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy:
Throughput oriented FPGA overlays using DSP blocks. DATE 2016: 1628-1633 - [c3]Abhishek Kumar Jain, Xiangwei Li, Pranjul Singhai, Douglas L. Maskell, Suhaib A. Fahmy:
DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect. FCCM 2016: 1-8 - [i1]Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy:
An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units. CoRR abs/1606.06460 (2016) - 2015
- [j2]Abhishek Kumar Jain, Xiangwei Li, Suhaib A. Fahmy, Douglas L. Maskell:
Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq. SIGARCH Comput. Archit. News 43(4): 28-33 (2015) - [c2]Abhishek Kumar Jain, Suhaib A. Fahmy, Douglas L. Maskell:
Efficient Overlay Architecture Based on DSP Blocks. FCCM 2015: 25-28 - 2014
- [j1]Abhishek Kumar Jain, Khoa Dang Pham, Jin Cui, Suhaib A. Fahmy, Douglas L. Maskell:
Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform. J. Signal Process. Syst. 77(1-2): 61-76 (2014) - 2013
- [c1]Khoa Dang Pham, Abhishek Kumar Jain, Jin Cui, Suhaib A. Fahmy, Douglas L. Maskell:
Microkernel hypervisor for a hybrid ARM-FPGA platform. ASAP 2013: 219-226
Coauthor Index
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