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ORCIDBing Li 0005
Person information
- affiliation: Technical University of Munich, Institute for Electronic Design Automation, Germany
Other persons with the same name
- Bing Li — disambiguation page
- Bing Li 0001
![[0000-0002-5888-6735]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-5888-6735")
— Chinese Academy of Sciences, Institute of Automation, National Laboratory of Pattern Recognition, Beijing, China (and 1 more) - Bing Li 0002 — Northeastern University, School of Information Science and Engineering, Shenyang, China
- Bing Li 0003 — Chongqing Jiaotong University, College of Sciences, China
- Bing Li 0004 — Shenzhen University, China (and 3 more)
- Bing Li 0006 — Hefei University of Technology, School of Electrical and Automation Engineering, China (and 1 more)
- Bing Li 0007 — Wuhan University of Technology, School of Economics, China (and 1 more)
- Bing Li 0008 — The City University of New York, Electrical Engineering Department, NY, USA
- Bing Li 0009 — University of Virginia, Charlottesville, VA, USA
- Bing Li 0010 — Wuhan University, School of Computer / State Key Lab of Software Engineering, China (and 1 more)
- Bing Li 0011 — Shenzhen University, College of Electronic Science and Technology, China (and 1 more)
- Bing Li 0012 — Georgia State University, Department of Computer Science, Atlanta, GA, USA
- Bing Li 0013 — ETH Zurich, Department of Mechanical and Process Engineering, Reliability and Risk Engineering Laboratory, Switzerland
- Bing Li 0014 — Qilu University of Technology (Shandong Academy of Sciences), School of Information, Jinan, China
- Bing Li 0015 — Harbin Institute of Technology, Department of Mechanical Engineering and Automation, Shenzhen, China (and 1 more)
- Bing Li 0016 — Southwest Jiaotong University, School of Electrical Engineering, Chengdu, China (and 2 more)
- Bing Li 0017 — Duke University, Durham, NC, USA (and 1 more)
- Bing Li 0018 — Lanzhou University, School of Information Science and Engineering, China
- Bing Li 0019 — Arizona State University, Tempe, USA
- Bing Li 0020 — Yunnan Minzu University, School of Mathematics and Computer Science, China
- Bing Li 0021 — Jilin University, College of Computer Science and Technology, Changchun, China
- Bing Li 0022 — Xi'an Jiaotong University, Institute of Microelectronics, China
- Bing Li 0023 — Xi'an Jiaotong University, State Key Laboratory for Manufacturing Systems Engineering, China
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2020 – today
- 2021
[j19]Chunfeng Liu, Xing Huang, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann:
DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1): 115-128 (2021)- 2020
- [j18]Qin Wang, Ulf Schlichtmann, Yici Cai, Weiqing Ji, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li:
Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 613-625 (2020) - [j17]Ying Zhu, Xing Huang, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann:
Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2489-2502 (2020) - [j16]Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann:
Test Generation for Flow-Based Microfluidic Biochips With General Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2530-2543 (2020) - [j15]Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann:
TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4482-4495 (2020) - [c53]Shuhang Zhang, Grace Li Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann:
Lifetime Enhancement for RRAM-based Computing-In-Memory Engine Considering Aging and Thermal Effects. AICAS 2020: 11-15 - [c52]Grace Li Zhang, Michaela Brunner, Bing Li, Georg Sigl, Ulf Schlichtmann:
Timing Resilience for Efficient and Secure Circuits. ASP-DAC 2020: 623-628 - [c51]Gautam Choudhary, Sandeep Pal, Debraj Kundu, Sukanta Bhattacharjee, Shigeru Yamashita, Bing Li, Ulf Schlichtmann, Sudip Roy:
Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays. DATE 2020: 1335-1338 - [c50]Shuhang Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann:
A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines. DATE 2020: 1426-1431 - [c49]Ying Zhu, Grace Li Zhang, Tianchen Wang, Bing Li, Yiyu Shi, Tsung-Yi Ho, Ulf Schlichtmann:
Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and Noise. DATE 2020: 1590-1593 - [c48]Grace Li Zhang, Bing Li, Ying Zhu, Shuhang Zhang, Tianchen Wang, Yiyu Shi, Tsung-Yi Ho, Hai (Helen) Li, Ulf Schlichtmann:
Reliable and Robust RRAM-based Neuromorphic Computing. ACM Great Lakes Symposium on VLSI 2020: 33-38 - [c47]Xing Huang, Youlin Pan, Grace Li Zhang, Bing Li, Wenzhong Guo, Tsung-Yi Ho, Ulf Schlichtmann:
PathDriver: A Path-Driven Architectural Synthesis Flow for Continuous-Flow Microfluidic Biochips. ICCAD 2020: 29:1-29:8 - [c46]Ying Zhu, Grace Li Zhang, Bing Li, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Tsung-Yi Ho, Ulf Schlichtmann:
Countering Variations and Thermal Effects for Accurate Optical Neural Networks. ICCAD 2020: 152:1-152:7 - [i19]Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann:
TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix). CoRR abs/2003.00862 (2020)
2010 – 2019
- 2019
- [j14]Grace Li Zhang, Bing Li, Yiyu Shi, Jiang Hu, Ulf Schlichtmann:
EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 705-718 (2019) - [c45]Xing Huang, Tsung-Yi Ho, Wenzhong Guo, Bing Li, Ulf Schlichtmann:
MiniControl: Synthesis of Continuous-Flow Microfluidics with Strictly Constrained Control Ports. DAC 2019: 145 - [c44]Zhisheng Chen, Xing Huang, Wenzhong Guo, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Physical Synthesis of Flow-Based Microfluidic Biochips Considering Distributed Channel Storage. DATE 2019: 1525-1530 - [c43]Yu-Huei Lin, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann:
Block-Flushing: A Block-based Washing Algorithm for Programmable Microfluidic Devices. DATE 2019: 1531-1536 - [c42]Alessandro Bernardini, Chunfeng Liu, Bing Li, Ulf Schlichtmann:
Fault Localization in Programmable Microfluidic Devices. DATE 2019: 1607-1610 - [c41]Shuhang Zhang, Grace Li Zhang, Bing Li, Hai Helen Li, Ulf Schlichtmann:
Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing. DATE 2019: 1751-1756 - 2018
- [j13]Bing Li, Masanori Hashimoto, Ulf Schlichtmann:
From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018) - [j12]Alessandro Bernardini, Chunfeng Liu, Bing Li, Ulf Schlichtmann:
Efficient spanning-tree-based test pattern generation for Programmable Microfluidic Devices. Microelectron. J. 79: 38-45 (2018) - [j11]Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi, Ulf Schlichtmann:
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 392-405 (2018) - [j10]Tsun-Ming Tseng, Mengchu Li, Daniel Nestor Freitas, Travis McAuley, Bing Li, Tsung-Yi Ho, Ismail Emre Araci, Ulf Schlichtmann:
Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1588-1601 (2018) - [c40]Grace Li Zhang, Bing Li, Masanori Hashimoto, Ulf Schlichtmann:
Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units. DAC 2018: 26:1-26:6 - [c39]Yu-Kai Chuang, Kuan-Jung Chen, Kun-Lin Lin, Shao-Yun Fang, Bing Li, Ulf Schlichtmann:
PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip. DAC 2018: 151:1-151:6 - [c38]Chunfeng Liu, Bing Li, Tsung-Yi Ho, Krishnendu Chakrabarty, Ulf Schlichtmann:
Design-for-testability for continuous-flow microfluidic biochips. DAC 2018: 164:1-164:6 - [c37]Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann:
TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing. DATE 2018: 91-96 - [c36]Robert Wille, Bing Li, Rolf Drechsler, Ulf Schlichtmann:
Automatic Design of Microfluidic Devices. FDL 2018: 5-16 - [c35]Ying Zhu, Bing Li, Tsung-Yi Ho, Qin Wang, Hailong Yao, Robert Wille, Ulf Schlichtmann:
Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips. ICCAD 2018: 123 - [c34]Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann:
Test generation for microfluidic fully programmable valve arrays (FPVAs) with heuristic acceleration. ICICDT 2018: 97-100 - [c33]Fengxian Jiao, Sheqin Dong, Bei Yu, Bing Li, Ulf Schlichtmann:
Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips. ISCAS 2018: 1-4 - [c32]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security. ISVLSI 2018: 715-718 - 2017
- [j9]Qin Wang, Yue Xu, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai:
Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips. IEEE Trans. Biomed. Circuits Syst. 11(6): 1488-1499 (2017) - [j8]Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann:
An Efficient Two-Phase ILP-Based Algorithm for Precise CMOS RFIC Layout Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(8): 1313-1326 (2017) - [c31]Qin Wang, Shiliang Zuo, Hailong Yao, Tsung-Yi Ho, Bing Li, Ulf Schlichtmann, Yici Cai:
Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips. ASP-DAC 2017: 524-529 - [c30]Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann:
Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. DAC 2017: 49:1-49:6 - [c29]Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling. DAC 2017: 51:1-51:6 - [c28]Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann:
Testing microfluidic Fully Programmable Valve Arrays (FPVAs). DATE 2017: 91-96 - [c27]Bing Li, Ulf Schlichtmann:
Reliability-aware synthesis and fault test of fully programmable valve arrays (FPVAs). DFT 2017: 1 - [c26]Bing Li:
W3B: Special session: Secure multi-processors systems-on-chip for critical applications. SoCC 2017: 1 - [c25]Robert Wille, Bing Li:
Design automation for Labs-on-Chip: A new "playground" for SoC designers. SoCC 2017: 1-2 - [c24]Baris Yigit, Grace Li Zhang, Bing Li, Yiyu Shi, Ulf Schlichtmann:
Application of machine learning methods in post-silicon yield improvement. SoCC 2017: 243-248 - [i18]Bing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann:
Static Timing Model Extraction for Combinational Circuits. CoRR abs/1705.02610 (2017) - [i17]Bing Li, Ning Chen, Manuel Schmidt, Walter Schneider, Ulf Schlichtmann:
On Hierarchical Statistical Static Timing Analysis. CoRR abs/1705.04975 (2017) - [i16]Bing Li, Ning Chen, Ulf Schlichtmann:
Timing Model Extraction for Sequential Circuits Considering Process Variations. CoRR abs/1705.04976 (2017) - [i15]Bing Li, Ning Chen, Ulf Schlichtmann:
Fast Statistical Timing Analysis for Circuits with Post-Silicon Tunable Clock Buffers. CoRR abs/1705.04979 (2017) - [i14]Bing Li, Ning Chen, Ulf Schlichtmann:
Statistical Timing Analysis for Latch-Controlled Circuits with Reduced Iterations and Graph Transformations. CoRR abs/1705.04980 (2017) - [i13]Bing Li, Ning Chen, Yang Xu, Ulf Schlichtmann:
On Timing Model Extraction and Hierarchical Statistical Timing Analysis. CoRR abs/1705.04981 (2017) - [i12]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Post-Route Refinement for High-Frequency PCBs Considering Meander Segment Alleviation. CoRR abs/1705.04982 (2017) - [i11]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Post-Route Alleviation of Dense Meander Segments in High-Performance Printed Circuit Boards. CoRR abs/1705.04983 (2017) - [i10]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
ILP-based Alleviation of Dense Meander Segments with Prioritized Shifting and Progressive Fixing in PCB Routing. CoRR abs/1705.04984 (2017) - [i9]Bing Li, Ulf Schlichtmann:
Statistical Timing Analysis and Criticality Computation for Circuits with Post-Silicon Clock Tuning Elements. CoRR abs/1705.04986 (2017) - [i8]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Storage and Caching: Synthesis of Flow-based Microfluidic Biochips. CoRR abs/1705.04988 (2017) - [i7]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability. CoRR abs/1705.04990 (2017) - [i6]Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann:
Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing. CoRR abs/1705.04991 (2017) - [i5]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers. CoRR abs/1705.04992 (2017) - [i4]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model. CoRR abs/1705.04993 (2017) - [i3]Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi, Ulf Schlichtmann:
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. CoRR abs/1705.04995 (2017) - [i2]Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann:
Testing Microfluidic Fully Programmable Valve Arrays (FPVAs). CoRR abs/1705.04996 (2017) - [i1]Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann:
Transport or Store? Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. CoRR abs/1705.04998 (2017) - 2016
- [j7]Tsun-Ming Tseng, Bing Li, Mengchu Li, Tsung-Yi Ho, Ulf Schlichtmann:
Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid Routing for Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 1981-1994 (2016) - [c23]Ulf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li:
Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits. ASP-DAC 2016: 705-711 - [c22]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers. DAC 2016: 60:1-60:6 - [c21]Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann:
Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing. DAC 2016: 101:1-101:6 - [c20]Tsun-Ming Tseng, Mengchu Li, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Columba: co-layout synthesis for continuous-flow microfluidic biochips. DAC 2016: 147:1-147:6 - [c19]Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitations. DATE 2016: 624-629 - [c18]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Sampling-based buffer insertion for post-silicon yield improvement under process variability. DATE 2016: 1457-1460 - [c17]Grace Li Zhang, Bing Li, Ulf Schlichtmann:
PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model. ICCAD 2016: 100 - [c16]Qin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai:
Control-fluidic CoDesign for paper-based digital microfluidic biochips. ICCAD 2016: 103 - [c15]Robert Wille, Bing Li, Ulf Schlichtmann, Rolf Drechsler:
From biochips to quantum circuits: computer-aided design for emerging technologies. ICCAD 2016: 132 - 2015
- [j6]Tsun-Ming Tseng, Bing Li, Ulf Schlichtmann, Tsung-Yi Ho:
Storage and Caching: Synthesis of Flow-Based Microfluidic Biochips. IEEE Des. Test 32(6): 69-75 (2015) - [j5]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(6): 1000-1013 (2015) - [j4]Bing Li, Ulf Schlichtmann:
Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1784-1797 (2015) - [c14]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping. DAC 2015: 141:1-141:6 - [c13]Rohit Kumar, Bing Li, Yiren Shen, Ulf Schlichtmann, Jiang Hu:
Timing verification for adaptive integrated circuits. DATE 2015: 1587-1590 - 2013
- [j3]Bing Li, Ning Chen, Yang Xu, Ulf Schlichtmann:
On Timing Model Extraction and Hierarchical Statistical Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 367-380 (2013) - [c12]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Post-route refinement for high-frequency PCBs considering meander segment alleviation. ACM Great Lakes Symposium on VLSI 2013: 323-324 - [c11]Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Post-route alleviation of dense meander segments in high-performance printed circuit boards. ICCAD 2013: 713-720 - 2012
- [j2]Ning Chen, Bing Li, Ulf Schlichtmann:
Iterative timing analysis based on nonlinear and interdependent flipflop modelling. IET Circuits Devices Syst. 6(5): 330-337 (2012) - [j1]Bing Li, Ning Chen, Ulf Schlichtmann:
Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(11): 1670-1683 (2012) - [c10]Yang Xu, Bing Li, Ralph Hasholzner, Bernhard Rohfleisch, Christian Haubelt, Jürgen Teich:
Variation-aware leakage power model extraction for system-level hierarchical power analysis. DATE 2012: 346-351 - 2011
- [c9]Bing Li, Ning Chen:
Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers. ICCAD 2011: 111-117 - [c8]Ning Chen, Bing Li, Ulf Schlichtmann:
Timing Modeling of Flipflops Considering Aging Effects. PATMOS 2011: 63-72 - [c7]Ning Chen, Bing Li, Ulf Schlichtmann:
Iterative Timing Analysis Considering Interdependency of Setup and Hold Times. PATMOS 2011: 73-82 - 2010
- [c6]Bing Li, Ning Chen, Ulf Schlichtmann:
Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods. ICCAD 2010: 524-531
2000 – 2009
- 2009
- [c5]Bing Li, Ning Chen, Manuel Schmidt, Walter Schneider, Ulf Schlichtmann:
On hierarchical statistical static timing analysis. DATE 2009: 1320-1325 - [c4]Bing Li, Ning Chen, Ulf Schlichtmann:
Timing model extraction for sequential circuits considering process variations. ICCAD 2009: 333-343 - [c3]Ning Chen, Bing Li, Ulf Schlichtmann:
Sensitivity based parameter reduction for statistical analysis of circuit performance. ICECS 2009: 443-446 - 2008
- [c2]Bing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann:
Static Timing Model Extraction for Combinational Circuits. PATMOS 2008: 156-166 - [c1]Walter Schneider, Manuel Schmidt, Bing Li, Ulf Schlichtmann:
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA. PATMOS 2008: 167-177
Coauthor Index
[j19] [j18] [j17] [j16] [j15] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [i19] [j14] [c45] [c44] [c43] [c42] [c41] [j13] [j12] [j11] [j10] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [j9] [j8] [c31] [c30] [c29] [c28] [c27] [c24] [i18] [i17] [i16] [i15] [i14] [i13] [i12] [i11] [i10] [i9] [i8] [i7] [i6] [i5] [i4] [i3] [i2] [i1] [j7] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [j6] [j5] [j4] [c14] [c13] [j3] [c12] [c11] [j2] [j1] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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