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ORCIDZhongfeng Wang 0001
王中风
Person information
- unicode name: 王中风
- affiliation: Nanjing University, School of Electronic Science and Engineering, Nanjing, China
- affiliation (former): Broadcom Corporation, San Jose, CA, USA
- affiliation (former): Oregon State University, Corvallis, OR, USA
- affiliation (former, PhD 2000): University of Minnesota, Minneapolis, MN, USA
Other persons with the same name
- Zhongfeng Wang (aka: Zhong-feng Wang) — disambiguation page
- Zhongfeng Wang 0002
![[0000-0003-0402-7334]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-0402-7334")
— Shenyang Institute of Automation, Key Laboratory of Networked Control Systems, Shenyang, China (and 1 more)
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2020 – today
- 2024
[j154]Rongjie Wan, Yuxing Chen, Suwen Song, Zhongfeng Wang:
CSI-Based MIMO Indoor Positioning Using Attention-Aided Deep Learning. IEEE Commun. Lett. 28(1): 53-57 (2024)- [j153]Yangcan Zhou, Zijian Qin, Zhongfeng Wang:
Efficient Soft-Cancellation Flip Decoding of Polar Codes. IEEE Commun. Lett. 28(8): 1745-1749 (2024) - [j152]Xuewen He, Yichuan Bai, Yujia Liu, Li Du, Zhongfeng Wang, Yuan Du:
Low-Latency PAE: Permutation-Based Address Encryption Hardware Engine for IoT Real-Time Memory Protection. IEEE Internet Things J. 11(7): 12319-12330 (2024) - [j151]Yuxing Chen, Xinrui Wang, Suwen Song, Lang Feng, Zhongfeng Wang:
RISC-V Custom Instructions of Elementary Functions for IoT Endpoint Devices. IEEE Trans. Computers 73(2): 523-535 (2024) - [j150]Luyi Li, Jiayi Huang, Lang Feng, Zhongfeng Wang:
Prefender: A Prefetching Defender Against Cache Side Channel Attacks as a Pretender. IEEE Trans. Computers 73(6): 1457-1471 (2024) - [j149]Chao Fang, Wei Sun, Aojun Zhou, Zhongfeng Wang:
Efficient N:M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 506-519 (2024) - [j148]Huihong Shi, Yang Xu, Yuefei Wang, Wendong Mao, Zhongfeng Wang:
NASA-F: FPGA-Oriented Search and Acceleration for Multiplication-Reduced Hybrid Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 306-319 (2024) - [j147]Jinming Lu, Hui Wang, Jun Lin, Zhongfeng Wang:
WinTA: An Efficient Reconfigurable CNN Training Accelerator With Decomposition Winograd. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 634-645 (2024) - [j146]Yangyang Chen, Huiyu Feng, Suwen Song, Zhongfeng Wang:
Correlated Channel-Oriented Expectation Propagation-Based Detector for Massive MIMO Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1429-1442 (2024) - [j145]Yuxing Chen, Zhongfeng Wang:
A Heterogeneous and Reconfigurable Decoder for the IEEE 1901 Standard. IEEE Trans. Circuits Syst. I Regul. Pap. 71(10): 4767-4777 (2024) - [j144]Wendong Mao, Meiqi Wang, Xiaoru Xie, Xiao Wu, Zhongfeng Wang:
Hardware Accelerator Design for Sparse DNN Inference and Training: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1708-1714 (2024) - [j143]Ke Tang, Lang Feng, Zhongfeng Wang:
Mixed Integer Programming based Placement Refinement by RSMT Model with Movable Pins. ACM Trans. Design Autom. Electr. Syst. 29(2): 36:1-36:18 (2024) - [j142]Xiao Hu, Zhihao Li, Zhongfeng Wang, Xianhui Lu:
ALT: Area-Efficient and Low-Latency FPGA Design for Torus Fully Homomorphic Encryption. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 645-657 (2024) - [j141]Xiao Wu, Miaoxin Wang, Jun Lin, Zhongfeng Wang:
Amoeba: An Efficient and Flexible FPGA-Based Accelerator for Arbitrary-Kernel CNNs. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1086-1099 (2024) - [j140]Baoling Hong, Haikuo Shao, Zhongfeng Wang:
A Low Complexity Online Learning Approximate Message Passing Detector for Massive MIMO. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1273-1284 (2024) - [j139]Huihong Shi, Xin Cheng, Wendong Mao, Zhongfeng Wang:
P2-ViT: Power-of-Two Post-Training Quantization and Acceleration for Fully Quantized Vision Transformer. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1704-1717 (2024) - [c197]Qiwei Dong, Xiaoru Xie, Zhongfeng Wang:
SWAT: An Efficient Swin Transformer Accelerator Based on FPGA. ASPDAC 2024: 515-520 - [c196]Longwei Huang, Chao Fang, Qiong Li, Jun Lin, Zhongfeng Wang:
A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge. ASPDAC 2024: 927-932 - [c195]Siyu Zhang, Wendong Mao, Huihong Shi, Zhongfeng Wang:
A Computationally Efficient Neural Video Compression Accelerator Based on a Sparse CNN-Transformer Hybrid Network. DATE 2024: 1-6 - [c194]Binqiang Dan, Hui Qian, Zhongfeng Wang:
A High Dynamic Range Feedback Compensation Front-End for Unlimited Sampling ASDM ADC. ISCAS 2024: 1-5 - [c193]Jinjie Hu, Suwen Song, Zhongfeng Wang:
A Novel Low-Complexity Massive MIMO Detector with Near-Optimum Performance. ISCAS 2024: 1-5 - [c192]Yuhao Ji, Chao Fang, Zhongfeng Wang:
BETA: Binarized Energy-Efficient Transformer Accelerator at the Edge. ISCAS 2024: 1-5 - [c191]Xinyan Liu, Xiao Wu, Haikuo Shao, Zhongfeng Wang:
A Flexible FPGA-Based Accelerator for Efficient Inference of Multi-Precision CNNs. ISCAS 2024: 1-5 - [c190]Haikuo Shao, Huihong Shi, Wendong Mao, Zhongfeng Wang:
An FPGA-Based Reconfigurable Accelerator for Convolution-Transformer Hybrid EfficientViT. ISCAS 2024: 1-5 - [c189]Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin:
A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. ISCAS 2024: 1-5 - [c188]Miaoxin Wang, Xiao Wu, Jun Lin, Zhongfeng Wang:
An FPGA-Based Accelerator Enabling Efficient Support for CNNs with Arbitrary Kernel Sizes. ISCAS 2024: 1-5 - [c187]Haoran Zeng, Wendong Mao, Siyu Zhang, Zhongfeng Wang:
A Precision-Scalable Vision Accelerator for Robotic Applications. ISCAS 2024: 1-5 - [i37]Yuhao Ji, Chao Fang, Zhongfeng Wang:
BETA: Binarized Energy-Efficient Transformer Accelerator at the Edge. CoRR abs/2401.11851 (2024) - [i36]Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin:
A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. CoRR abs/2401.16872 (2024) - [i35]Miaoxin Wang, Xiao Wu, Jun Lin, Zhongfeng Wang:
An FPGA-Based Accelerator Enabling Efficient Support for CNNs with Arbitrary Kernel Sizes. CoRR abs/2402.14307 (2024) - [i34]Haikuo Shao, Huihong Shi, Wendong Mao, Zhongfeng Wang:
An FPGA-Based Reconfigurable Accelerator for Convolution-Transformer Hybrid EfficientViT. CoRR abs/2403.20230 (2024) - [i33]Huihong Shi, Haikuo Shao, Wendong Mao, Zhongfeng Wang:
Trio-ViT: Post-Training Quantization and Acceleration for Softmax-Free Efficient Vision Transformer. CoRR abs/2405.03882 (2024) - [i32]Huihong Shi, Xin Cheng, Wendong Mao, Zhongfeng Wang:
P2-ViT: Power-of-Two Post-Training Quantization and Acceleration for Fully Quantized Vision Transformer. CoRR abs/2405.19915 (2024) - [i31]Yuhao Ji, Chao Fang, Shaobo Ma, Haikuo Shao, Zhongfeng Wang:
Co-Designing Binarized Transformer and Hardware Accelerator for Efficient End-to-End Edge Deployment. CoRR abs/2407.12070 (2024) - [i30]Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin:
SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. CoRR abs/2409.14017 (2024) - [i29]Jing Tian, Bo Wu, Lang Feng, Haochen Zhang, Zhongfeng Wang:
A Fast and Efficient SIKE Co-Design: Coarse-Grained Reconfigurable Accelerators with Custom RISC-V Microcontroller on FPGA. IACR Cryptol. ePrint Arch. 2024: 1120 (2024) - 2023
- [j138]Yangcan Zhou, Yaojie Zheng, Zhongfeng Wang:
Fast Successive-Cancellation Decoding of 5G Parity-Check Polar Codes. IEEE Commun. Lett. 27(1): 37-40 (2023) - [j137]Shangpeng Deng, Zhiyuan Xiao, Jin Sha, Zhongfeng Wang:
An Adaptive Chase-Pyndiah Algorithm for Turbo Product Codes. IEEE Commun. Lett. 27(4): 1065-1069 (2023) - [j136]Yuxing Chen, Xinyuan Qiao, Keyue Deng, Suwen Song, Zhongfeng Wang:
3.8-Gbps Polar Belief Propagation Decoder on GPU. IEEE Commun. Lett. 27(5): 1247-1251 (2023) - [j135]Danyang Zhu, Jing Tian, Minghao Li, Zhongfeng Wang:
Low-latency Hardware Architecture for VDF Evaluation in Class Groups. IEEE Trans. Computers 72(6): 1706-1717 (2023) - [j134]Minghao Li, Jing Tian, Xiao Hu, Zhongfeng Wang:
Reconfigurable and High-Efficiency Polynomial Multiplication Accelerator for CRYSTALS-Kyber. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2540-2551 (2023) - [j133]Xinrui Wang, Lang Feng, Zhongfeng Wang:
ProMiSE: A High-Performance Programmable Hardware Monitor for High Security Enforcement of Software Execution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3599-3612 (2023) - [j132]Lang Feng, Jin Sha, Zhongfeng Wang:
1+1 <2: Efficient Automatic Standard Cell Sharing Between Digital VLSI Designs for Area Saving. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4177-4190 (2023) - [j131]Yifeng Song, Xiao Hu, Jing Tian, Zhongfeng Wang:
A High-Speed FPGA-Based Hardware Implementation for Leighton-Micali Signature. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 241-252 (2023) - [j130]Xiao Hu, Jing Tian, Minghao Li, Zhongfeng Wang:
AC-PM: An Area-Efficient and Configurable Polynomial Multiplier for Lattice Based Cryptography. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 719-732 (2023) - [j129]Siyu Zhang, Wendong Mao, Zhongfeng Wang:
An Efficient Accelerator Based on Lightweight Deformable 3D-CNN for Video Super-Resolution. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2384-2397 (2023) - [j128]Huihong Shi, Haoran You, Zhongfeng Wang, Yingyan Lin:
NASA+: Neural Architecture Search and Acceleration for Multiplication-Reduced Hybrid Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2523-2536 (2023) - [j127]Yue Geng, Xiao Hu, Minghao Li, Zhongfeng Wang:
Rethinking Parallel Memory Access Pattern in Number Theoretic Transform Design. IEEE Trans. Circuits Syst. II Express Briefs 70(5): 1689-1693 (2023) - [j126]Xiao Wu, Shuang Liang, Meiqi Wang, Zhongfeng Wang:
ReAFM: A Reconfigurable Nonlinear Activation Function Module for Neural Networks. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2660-2664 (2023) - [j125]Lun Ou, Danyang Zhu, Jing Tian, Zhongfeng Wang:
Fast Hardware Implementation for Extended GCD of Large Numbers in Redundant Representation. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 3094-3098 (2023) - [j124]Wendong Mao, Ziqi Su, Jiapeng Luo, Zhongfeng Wang:
A Unified Acceleration Solution Based on Deformable Network for Image Pixel Processing. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3629-3633 (2023) - [j123]Yue Yu, Wendong Mao, Jiapeng Luo, Zhongfeng Wang:
A Low-Latency Framework With Algorithm-Hardware Co-Optimization for 3-D Point Cloud. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 4221-4225 (2023) - [j122]Danyang Zhu, Rongrong Zhang, Lun Ou, Jing Tian, Zhongfeng Wang:
Low-Latency Design and Implementation of the Squaring in Class Groups for Verifiable Delay Function Using Redundant Representation. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2023(1): 438-462 (2023) - [j121]Meiqi Wang, Tianqi Su, Siyi Chen, Wenhan Yang, Jiaying Liu, Zhongfeng Wang:
Automatic Model-Based Dataset Generation for High-Level Vision Tasks of Autonomous Driving in Haze Weather. IEEE Trans. Ind. Informatics 19(8): 9071-9081 (2023) - [j120]Wendong Mao, Shuai Yang, Huihong Shi, Jiaying Liu, Zhongfeng Wang:
Intelligent Typography: Artistic Text Style Transfer for Complex Texture and Structure. IEEE Trans. Multim. 25: 6485-6498 (2023) - [j119]Wendong Mao, Peixiang Yang, Zhongfeng Wang:
FTA-GAN: A Computation-Efficient Accelerator for GANs With Fast Transformation Algorithm. IEEE Trans. Neural Networks Learn. Syst. 34(6): 2978-2992 (2023) - [j118]Jinming Lu, Chao Ni, Zhongfeng Wang:
ETA: An Efficient Training Accelerator for DNNs Based on Hardware-Algorithm Co-Optimization. IEEE Trans. Neural Networks Learn. Syst. 34(10): 7660-7674 (2023) - [j117]Lang Feng, Wenjian Liu, Chuliang Guo, Ke Tang, Cheng Zhuo, Zhongfeng Wang:
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design. ACM Trans. Design Autom. Electr. Syst. 28(3): 35:1-35:20 (2023) - [j116]Suwen Song, Lu Liu, Zhongfeng Wang, Juyan Xu:
Dual-Bit-Wise Stochastic Decoding for Polar Codes. IEEE Trans. Signal Process. 71: 512-524 (2023) - [j115]Siyuan Lu, Chenchen Zhou, Keli Xie, Jun Lin, Zhongfeng Wang:
Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT. IEEE Trans. Signal Process. 71: 3821-3834 (2023) - [j114]Yangyang Chen, Suwen Song, Zhongfeng Wang, Jun Lin:
An Efficient Massive MIMO Detector Based on Approximate Expectation Propagation. IEEE Trans. Very Large Scale Integr. Syst. 31(5): 696-700 (2023) - [j113]Rongrong She, Hui Qian, Zhongfeng Wang:
A New ACD-OMP Accelerator With Clustered Computing Look-Ahead. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1449-1453 (2023) - [j112]Haikuo Shao, Jinming Lu, Meiqi Wang, Zhongfeng Wang:
An Efficient Training Accelerator for Transformers With Hardware-Algorithm Co-Optimization. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1788-1801 (2023) - [c186]Chao Fang, Wei Sun, Aojun Zhou, Zhongfeng Wang:
CEST: Computation-Efficient N:M Sparse Training for Deep Neural Networks. DATE 2023: 1-2 - [c185]Jyotikrishna Dass, Shang Wu, Huihong Shi, Chaojian Li, Zhifan Ye, Zhongfeng Wang, Yingyan Lin:
ViTALiTy: Unifying Low-rank and Sparse Approximation for Vision Transformer Acceleration with a Linear Taylor Attention. HPCA 2023: 415-428 - [c184]Minghao She, Wendong Mao, Huihong Shi, Zhongfeng Wang:
S$$^2$$R: Exploring a Double-Win Transformer-Based Framework for Ideal and Blind Super-Resolution. ICANN (6) 2023: 522-537 - [c183]Jiayi Tian, Chao Fang, Haonan Wang, Zhongfeng Wang:
Bebert: Efficient And Robust Binary Ensemble Bert. ICASSP 2023: 1-5 - [c182]Qiong Li, Chao Fang, Zhongfeng Wang:
PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications. ISCAS 2023: 1-5 - [c181]Huiyang Xiong, Bohang Xiong, Wenhao Wang, Jing Tian, Hao Zhu, Zhongfeng Wang:
Efficient FPGA-Based Accelerator of the L-BFGS Algorithm for IoT Applications. ISCAS 2023: 1-5 - [c180]Yueqin Dai, Yifeng Song, Jing Tian, Zhongfeng Wang:
High-Throughput Hardware Implementation for Haraka in SPHINCS+. ISQED 2023: 1-6 - [c179]Xinyuan Qiao, Suwen Song, Jing Tian, Zhongfeng Wang:
Efficient Decryption Architecture for Classic McEliece. ISQED 2023: 1-7 - [c178]Changfu He, Keyue Deng, Suwen Song, Zhongfeng Wang:
Column-Weighted Probabilistic GDBF Decoder for Irregular LDPC Codes. ISVLSI 2023: 1-6 - [c177]Hui Wang, Jinming Lu, Jun Lin, Zhongfeng Wang:
An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd. ISVLSI 2023: 1-6 - [c176]Chen Li, Suwen Song, Jing Tian, Zhongfeng Wang, Çetin Kaya Koç:
An Efficient Hardware Design for Fast Implementation of HQC. SOCC 2023: 1-6 - [i28]Qiong Li, Chao Fang, Zhongfeng Wang:
PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications. CoRR abs/2302.01876 (2023) - [i27]Luyi Li, Jiayi Huang, Lang Feng, Zhongfeng Wang:
PREFENDER: A Prefetching Defender against Cache Side Channel Attacks as A Pretender. CoRR abs/2307.06756 (2023) - [i26]Minghao She, Wendong Mao, Huihong Shi, Zhongfeng Wang:
S2R: Exploring a Double-Win Transformer-Based Framework for Ideal and Blind Super-Resolution. CoRR abs/2308.08142 (2023) - [i25]Longwei Huang, Chao Fang, Qiong Li, Jun Lin, Zhongfeng Wang:
A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge. CoRR abs/2309.08186 (2023) - [i24]Chao Fang, Wei Sun, Aojun Zhou, Zhongfeng Wang:
Efficient N: M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design. CoRR abs/2309.13015 (2023) - [i23]Siyu Zhang, Wendong Mao, Huihong Shi, Zhongfeng Wang:
A Computationally Efficient Neural Video Compression Accelerator Based on a Sparse CNN-Transformer Hybrid Network. CoRR abs/2312.10716 (2023) - 2022
- [j111]Ruijia Yuan, Tianjiao Xie, Zhongfeng Wang:
A Reliability Profile Based Low-Complexity Dynamic Schedule LDPC Decoding. IEEE Access 10: 3390-3399 (2022) - [j110]Jiapeng Luo, Zhongfeng Wang:
Automatically search an optimal face detector for a specific deployment environment. EURASIP J. Adv. Signal Process. 2022(1): 43 (2022) - [j109]Baoling Hong, Hui Qian, Zhongfeng Wang:
Iterative Hard Thresholding Algorithm-Based Detector for Compressed OFDM-IM Systems. IEEE Commun. Lett. 26(9): 2205-2209 (2022) - [j108]Shuo Liang, Suipeng Xie, Xingcheng Liu, Zhongfeng Wang:
LDPC decoding with locally informed dynamic scheduling based on the law of large numbers. IET Commun. 16(6): 634-648 (2022) - [j107]Jiapeng Luo, Zhongfeng Wang:
A low latency traffic sign detection model with an automatic data labeling pipeline. Neural Comput. Appl. 34(18): 15499-15512 (2022) - [j106]Jing Tian, Piaoyang Wang, Zhe Liu, Jun Lin, Zhongfeng Wang, Johann Großschädl:
Efficient Software Implementation of the SIKE Protocol Using a New Data Representation. IEEE Trans. Computers 71(3): 670-683 (2022) - [j105]Lang Feng, Jiayi Huang, Luyi Li, Haochen Zhang, Zhongfeng Wang:
RvDfi: A RISC-V Architecture With Security Enforcement by High Performance Complete Data-Flow Integrity. IEEE Trans. Computers 71(10): 2499-2512 (2022) - [j104]Zhuang Shao, Xiaoliang Chen, Li Du, Lei Chen, Yuan Du, Wei Zhuang, Huadong Wei, Chenjia Xie, Zhongfeng Wang:
Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 668-681 (2022) - [j103]Xiao Wu, Yufei Ma, Meiqi Wang, Zhongfeng Wang:
A Flexible and Efficient FPGA Accelerator for Various Large-Scale and Lightweight CNNs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1185-1198 (2022) - [j102]Suwen Song, Zhongfeng Wang:
An Area-Efficient Message Passing Detector for Massive MIMO Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1751-1764 (2022) - [j101]Zhiyuan Chen, Yufei Ma, Zhongfeng Wang:
Hybrid Stochastic-Binary Computing for Low-Latency and High-Precision Inference of CNNs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2707-2720 (2022) - [j100]Yuxing Chen, Hangxuan Cui, Zhongfeng Wang:
High-Throughput LDPC-CC Decoders Based on Storage, Arithmetic, and Control Improvements. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1069-1073 (2022) - [j99]Meiqi Wang, Xin Cheng, Dingyang Zou, Zhongfeng Wang:
FACCU: Enable Fast Accumulation for High-Speed DSP Systems. IEEE Trans. Circuits Syst. II Express Briefs 69(12): 4634-4638 (2022) - [j98]Meiqi Wang, Liulu He, Jun Lin, Zhongfeng Wang:
Rethinking Adaptive Computing: Building a Unified Model Complexity-Reduction Framework With Adversarial Robustness. IEEE Trans. Neural Networks Learn. Syst. 33(4): 1803-1810 (2022) - [j97]Jinming Lu, Jian Huang, Zhongfeng Wang:
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration. IEEE Trans. Very Large Scale Integr. Syst. 30(8): 1034-1046 (2022) - [j96]Yichuan Bai, Mingzhe Jiang, Qingyu Zhu, Xiaoliang Chen, Yuan Du, Li Du, Zhongfeng Wang:
An Efficient High-Throughput Structured-Light Depth Engine. IEEE Trans. Very Large Scale Integr. Syst. 30(8): 1047-1058 (2022) - [j95]Yuxing Chen, Hangxuan Cui, Zhongfeng Wang:
An Efficient Reconfigurable Encoder for the IEEE 1901 Standard. IEEE Trans. Very Large Scale Integr. Syst. 30(9): 1368-1372 (2022) - [j94]Suwen Song, Hangxuan Cui, Zhongfeng Wang:
A Universal Efficient Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1553-1557 (2022) - [j93]Chao Fang, Aojun Zhou, Zhongfeng Wang:
An Algorithm-Hardware Co-Optimized Framework for Accelerating N: M Sparse Transformers. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1573-1586 (2022) - [j92]Xiao Hu, Minghao Li, Jing Tian, Zhongfeng Wang:
Efficient Homomorphic Convolution Designs on FPGA for Secure Inference. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1691-1704 (2022) - [c175]Mingyang Xu, Jinming Lu, Zhongfeng Wang, Jun Lin:
An Efficient CNN Training Accelerator Leveraging Transposable Block Sparsity. AICAS 2022: 230-233 - [c174]Lu Liu, Suwen Song, Zhongfeng Wang:
A Novel Interleaving Scheme for Concatenated Codes on Burst-Error Channel. APCC 2022: 309-314 - [c173]Keyue Deng, Xinyuan Qiao, Yuxing Chen, Suwen Song, Zhongfeng Wang:
Performance Analysis of Extended Integrated Interleaved Codes. APCC 2022: 498-503 - [c172]Minghao Li, Jing Tian, Xiao Hu, Yuan Cao, Zhongfeng Wang:
High-Speed and Low-Complexity Modular Reduction Design for CRYSTALS-Kyber. APCCAS 2022: 1-5 - [c171]Xinyuan Qiao, Keyue Deng, Yuxing Chen, Suwen Song, Zhongfeng Wang:
Low-Complexity Parallel Syndrome Computation for BCH Decoders Based on Cyclotomic FFT. APCCAS 2022: 350-354 - [c170]Qinyuan Zhang, Suwen Song, Zhongfeng Wang:
Low-Complexity Dynamic Single-Minimum Min-Sum Algorithm and Hardware Implementation for LDPC Codes. APCCAS 2022: 389-393 - [c169]Xun Jiang, Jiarui Wang, Yibo Lin, Zhongfeng Wang:
FPGA-Accelerated Maze Routing Kernel for VLSI Designs. ASP-DAC 2022: 592-597 - [c168]Keli Xie, Dongchen He, Jiaxin Zhuang, Siyuan Lu, Zhongfeng Wang:
View Dialogue in 2D: A Two-stream Model in Time-speaker Perspective for Dialogue Summarization and beyond. COLING 2022: 6075-6088 - [c167]Luyi Li, Jiayi Huang, Lang Feng, Zhongfeng Wang:
PREFENDER: A Prefetching Defender against Cache Side Channel Attacks as A Pretender. DATE 2022: 1509-1514 - [c166]Ruixin Xue, Meiqi Wang, Zhongfeng Wang:
Boosting Both Robustness and Hardware Efficiency via Random Pruning Mask Selection. ICANN (1) 2022: 49-60 - [c165]Huihong Shi, Haoran You, Yang Zhao, Zhongfeng Wang, Yingyan Lin:
NASA: Neural Architecture Search and Acceleration for Hardware Inspired Hybrid Networks. ICCAD 2022: 58:1-58:9 - [c164]Xin Cheng, Meiqi Wang, Yu-Bo Shi, Jun Lin, Zhongfeng Wang:
Magical-Decomposition: Winning Both Adversarial Robustness and Efficiency on Hardware. ICMLC 2022: 61-66 - [c163]Ziqi Su, Wendong Mao, Zhongfeng Wang, Jun Lin, Wenqiang Wang, Haitao Sun:
Accelerate Three-Dimensional Generative Adversarial Networks Using Fast Algorithm. ISCAS 2022: 31-35 - [c162]HongRui Song, Ya Wang, Meiqi Wang, Zhongfeng Wang:
UCViT: Hardware-Friendly Vision Transformer via Unified Compression. ISCAS 2022: 2022-2026 - [c161]Chao Fang, Shouliang Guo, Wei Wu, Jun Lin, Zhongfeng Wang, Ming Kai Hsu, Lingzhi Liu:
An Efficient Hardware Accelerator for Sparse Transformer Neural Networks. ISCAS 2022: 2670-2674 - [c160]Peixiang Yang, Wendong Mao, Zhongfeng Wang, Jun Lin:
A Reconfigurable Approach for Deconvolutional Network Acceleration with Fast Algorithm. ISCAS 2022: 2685-2689 - [c159]Jian Huang, Jinming Lu, Zhongfeng Wang:
An Efficient Hardware Architecture for DNN Training by Exploiting Triple Sparsity. ISCAS 2022: 2802-2805 - [c158]Bohang Xiong, Jing Tian, Zhongfeng Wang:
A High-Speed Codec Architecture for Lagrange Coded Computing. ISCAS 2022: 2811-2815 - [c157]Mingyu Zhu, Jiapeng Luo, Wendong Mao, Zhongfeng Wang:
An Efficient FPGA-based Accelerator for Deep Forest. ISCAS 2022: 3334-3338 - [c156]Chenjia Xie, Zhuang Shao, Hang Xu, Xiaoliang Chen, Li Du, Yuan Du, Zhongfeng Wang:
Deep Neural Network Interlayer Feature Map Compression Based on Least-Squares Fitting. ISCAS 2022: 3398-3402 - [c155]Siyu Zhang, Wendong Mao, Zhongfeng Wang:
An Efficient Accelerator of Deformable 3D Convolutional Network for Video Super-Resolution. ISVLSI 2022: 110-115 - [c154]Lei Yang, Jing Tian, Bo Wu, Zhongfeng Wang, Hao Ren:
An RS-BCH Concatenated FEC Code for Beyond 400 Gb/s Networking. ISVLSI 2022: 212-216 - [c153]Binjing Li, Siyuan Lu, Keli Xie, Zhongfeng Wang:
Accelerating NLP Tasks on FPGA with Compressed BERT and a Hardware-Oriented Early Exit Method. ISVLSI 2022: 410-413 - [c152]Lijuan Li, Hangxuan Cui, Yangcan Zhou, Zhongfeng Wang:
A Modified BP Bit-Flipping Algorithm for Polar Codes. SiPS 2022: 1-6 - [c151]Zilun Wang, Wendong Mao, Peixiang Yang, Zhongfeng Wang, Jun Lin:
An Efficient FPGA Accelerator for Point Cloud. SOCC 2022: 1-6 - [c150]Samira Carolina Oliva Madrigal, Gökay Saldamli, Chen Li, Yue Geng, Jing Tian, Zhongfeng Wang, Çetin Kaya Koç:
Reduction-Free Multiplication for Finite Fields and Polynomial Rings. WAIFI 2022: 53-78 - [c149]Ziyang Jiang, Siyuan Lu, Jun Lin, Zhongfeng Wang:
Forecasting Stock Indexes with Metabolic DWT and MWA-GM(1,1). WCSP 2022: 516-521 - [i22]Lang Feng, Wenjian Liu, Chuliang Guo, Ke Tang, Cheng Zhuo, Zhongfeng Wang:
GANDSE: Generative Adversarial Network based Design Space Exploration for Neural Network Accelerator Design. CoRR abs/2208.00800 (2022) - [i21]Chao Fang, Aojun Zhou, Zhongfeng Wang:
An Algorithm-Hardware Co-Optimized Framework for Accelerating N: M Sparse Transformers. CoRR abs/2208.06118 (2022) - [i20]Zilun Wang, Wendong Mao, Peixiang Yang, Zhongfeng Wang, Jun Lin:
An Efficient FPGA Accelerator for Point Cloud. CoRR abs/2210.07803 (2022) - [i19]Huihong Shi, Haoran You, Yang Zhao, Zhongfeng Wang, Yingyan Lin:
NASA: Neural Architecture Search and Acceleration for Hardware Inspired Hybrid Networks. CoRR abs/2210.13361 (2022) - [i18]Jiayi Tian, Chao Fang, Haonan Wang, Zhongfeng Wang:
BEBERT: Efficient and robust binary ensemble BERT. CoRR abs/2210.15976 (2022) - [i17]Mingyu Zhu, Jiapeng Luo, Wendong Mao, Zhongfeng Wang:
An Efficient FPGA-based Accelerator for Deep Forest. CoRR abs/2211.02281 (2022) - [i16]Jyotikrishna Dass, Shang Wu, Huihong Shi, Chaojian Li, Zhifan Ye, Zhongfeng Wang, Yingyan Lin:
ViTALiTy: Unifying Low-rank and Sparse Approximation for Vision Transformer Acceleration with a Linear Taylor Attention. CoRR abs/2211.05109 (2022) - [i15]Siyuan Lu, Chenchen Zhou, Keli Xie, Shiyi Liu, Jun Lin, Zhongfeng Wang:
Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT. CoRR abs/2211.08842 (2022) - [i14]Danyang Zhu, Jing Tian, Minghao Li, Zhongfeng Wang:
Low-latency Hardware Architecture for VDF Evaluation in Class Groups. IACR Cryptol. ePrint Arch. 2022: 755 (2022) - 2021
- [j91]Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang:
An Improved Reliability-Based Decoding Algorithm for NB-LDPC Codes. IEEE Commun. Lett. 25(4): 1153-1157 (2021) - [j90]Hangxuan Cui, Suwen Song, Zhongfeng Wang:
An Improved Method for Performance Analysis of Generalized Integrated Interleaved Codes. IEEE Commun. Lett. 25(10): 3166-3169 (2021) - [j89]Zhipeng Pan, Jing Lei, Lei Wen, Chaojing Tang, Zhongfeng Wang:
Low-complexity sphere decoding for MIMO-SCMA systems. IET Commun. 15(4): 537-545 (2021) - [j88]Jinming Lu, Chao Fang, Mingyang Xu, Jun Lin, Zhongfeng Wang:
Evaluations on Deep Neural Networks Training Using Posit Number System. IEEE Trans. Computers 70(2): 174-187 (2021) - [j87]Hangxuan Cui, Fakhreddine Ghaffari, Khoa Le, David Declercq, Jun Lin, Zhongfeng Wang:
Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 879-891 (2021) - [j86]Shuang Liang, Siyuan Lu, Jun Lin, Zhongfeng Wang:
Low-Latency Hardware Accelerator for Improved Engle-Granger Cointegration in Pairs Trading. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2911-2924 (2021) - [j85]Xiaoru Xie, Jun Lin, Zhongfeng Wang, Jinghe Wei:
An Efficient and Flexible Accelerator Design for Sparse Convolutional Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2936-2949 (2021) - [j84]Hui Qian, Xinxin Song, Dengji Li, Zhongfeng Wang:
Generalized Analog-to-Information Converter With Analysis Sparse Prior. IEEE Trans. Circuits Syst. I Regul. Pap. 68(9): 3574-3586 (2021) - [j83]Jing Tian, Bo Wu, Zhongfeng Wang:
High-Speed FPGA Implementation of SIKE Based on an Ultra-Low-Latency Modular Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. 68(9): 3719-3731 (2021) - [j82]Jing Tian, Jun Lin, Zhongfeng Wang:
Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 359-371 (2021) - [j81]Muhan Zheng, Yuanyong Luo, Hongbing Pan, Zhongfeng Wang, Yuan Xue:
CLA Formula and its Acceleration of Architecture Design for Clustered Look-Ahead Pipelined Recursive Digital Filter. J. Signal Process. Syst. 93(6): 617-629 (2021) - [c148]Tianqi Su, Meiqi Wang, Zhongfeng Wang:
Federated Regularization Learning: an Accurate and Safe Method for Federated Learning. AICAS 2021: 1-4 - [c147]Junhan Zhu, Xiaoliang Chen, Li Du, Haoran Geng, Yichuan Bai, Yuandong Li, Yuan Du, Zhongfeng Wang:
Flexible-width Bit-level Compressor for Convolutional Neural Network. AICAS 2021: 1-4 - [c146]Xiao Hu, Minghao Li, Jing Tian, Zhongfeng Wang:
DARM: A Low-Complexity and Fast Modular Multiplier for Lattice-Based Cryptography. ASAP 2021: 175-178 - [c145]Keli Xie, Siyuan Lu, Meiqi Wang, Zhongfeng Wang:
Elbert: Fast Albert with Confidence-Window Based Early Exit. ICASSP 2021: 7713-7717 - [c144]Huihong Shi, Wendong Mao, Zhongfeng Wang:
LITNet: A Light-weight Image Transform Net for Image Style Transfer. IJCNN 2021: 1-8 - [c143]Kai Chen, Yimin Huang, Yuan Du, Zhuang Shao, Xingyu Gu, Li Du, Zhongfeng Wang:
A DNN Optimization Framework with Unlabeled Data for Efficient and Accurate Reconfigurable Hardware Inference. ISCAS 2021: 1-5 - [c142]Chao Fang, Liulu He, Haonan Wang, Jinghe Wei, Zhongfeng Wang:
Accelerating 3D Convolutional Neural Networks Using 3D Fast Fourier Transform. ISCAS 2021: 1-5 - [c141]Yubo Shi, Meiqi Wang, Siyi Chen, Jinghe Wei, Zhongfeng Wang:
Transform-Based Feature Map Compression for CNN Inference. ISCAS 2021: 1-5 - [c140]Yifeng Song, Xiao Hu, Wenhao Wang, Jing Tian, Zhongfeng Wang:
High-Speed and Scalable FPGA Implementation of the Key Generation for the Leighton-Micali Signature Protocol. ISCAS 2021: 1-5 - [c139]Danyang Zhu, Jing Tian, Zhongfeng Wang:
Low-Latency Architecture for the Parallel Extended GCD Algorithm of Large Numbers. ISCAS 2021: 1-5 - [c138]Yimin Huang, Kai Chen, Zhuang Shao, Yichuan Bai, Yafeng Huang, Yuan Du, Li Du, Zhongfeng Wang:
LSMQ: A Layer-Wise Sensitivity-Based Mixed-Precision Quantization Method for Bit-Flexible CNN Accelerator. ISOCC 2021: 256-257 - [c137]Keyue Deng, Hangxuan Cui, Jun Lin, Zhongfeng Wang:
Counter Random Gradient Descent Bit-Flipping Decoder for LDPC Codes. ISVLSI 2021: 55-60 - [c136]Tongtong Yin, Wendong Mao, Jinming Lu, Zhongfeng Wang:
A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA. ISVLSI 2021: 144-149 - [c135]Luyi Li, Jun Lin, Zhongfeng Wang:
PipeBSW: A Two-Stage Pipeline Structure for Banded Smith-Waterman Algorithm on FPGA. ISVLSI 2021: 182-187 - [c134]Haikuo Shao, Jinming Lu, Jun Lin, Zhongfeng Wang:
An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training. ISVLSI 2021: 254-259 - [c133]Chunyu Wang, Jiapeng Luo, Zhongfeng Wang:
A Stage-wise Conversion Strategy for Low-Latency Deformable Spiking CNN. SiPS 2021: 1-6 - [c132]Shize Zhao, Liulu He, Xiaoru Xie, Jun Lin, Zhongfeng Wang:
Automatic Generation of Dynamic Inference Architecture for Deep Neural Networks. SiPS 2021: 117-122 - [c131]Yue Yu, Jiapeng Luo, Wendong Mao, Zhongfeng Wang:
A Memory-Efficient Hardware Architecture for Deformable Convolutional Networks. SiPS 2021: 140-145 - [i13]Keli Xie, Siyuan Lu, Meiqi Wang, Zhongfeng Wang:
Elbert: Fast Albert with Confidence-Window Based Early Exit. CoRR abs/2107.00175 (2021) - [i12]Zhuang Shao, Xiaoliang Chen, Li Du, Lei Chen, Yuan Du, Wei Zhuang, Huadong Wei, Chenjia Xie, Zhongfeng Wang:
Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression. CoRR abs/2110.06155 (2021) - [i11]Yifeng Song, Danyang Zhu, Jing Tian, Zhongfeng Wang:
A High-Speed Architecture for the Reduction in VDF Based on a Class Group. IACR Cryptol. ePrint Arch. 2021: 949 (2021) - 2020
- [j80]Zidi Qin, Yuou Qiu, Muhan Zheng, Hongxi Dong, Zhonghai Lu, Zhongfeng Wang, Hongbing Pan:
A Universal Approximation Method and Optimized Hardware Architectures for Arithmetic Functions Based on Stochastic Computing. IEEE Access 8: 46229-46241 (2020) - [j79]Wenjie Li, Jun Lin, Zhongfeng Wang:
Multi-Layer Generalized Integrated Interleaved Codes. IEEE Commun. Lett. 24(9): 1880-1884 (2020) - [j78]Yongsheng Yin, Kangkang Sun, Hongmei Chen, Xiaolei Wang, Lu Liu, Honghui Deng, Xu Meng, Kun Li, Zhongfeng Wang:
Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data. IEICE Electron. Express 17(3): 20190699 (2020) - [j77]Jiapeng Luo, Jiaying Liu, Jun Lin, Zhongfeng Wang:
A lightweight face detector by integrating the convolutional neural network with the image pyramid. Pattern Recognit. Lett. 133: 180-187 (2020) - [j76]Jing Tian, Suwen Song, Jun Lin, Zhongfeng Wang:
Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 57-61 (2020) - [j75]Yuxing Chen, Hangxuan Cui, Jun Lin, Zhongfeng Wang:
Fine-Grained Bit-Flipping Decoding for LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 67-II(5): 896-900 (2020) - [j74]Suwen Song, Hangxuan Cui, Jing Tian, Jun Lin, Zhongfeng Wang:
A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 67-II(8): 1399-1403 (2020) - [j73]Wenjian Liu, Jun Lin, Zhongfeng Wang:
A Precision-Scalable Energy-Efficient Convolutional Neural Network Accelerator. IEEE Trans. Circuits Syst. 67-I(10): 3484-3497 (2020) - [j72]Danyang Zhu, Siyuan Lu, Meiqi Wang, Jun Lin, Zhongfeng Wang:
Efficient Precision-Adjustable Architecture for Softmax Function in Deep Learning. IEEE Trans. Circuits Syst. 67-II(12): 3382-3386 (2020) - [j71]Zidi Qin, Yuou Qiu, Huaqing Sun, Zhonghai Lu, Zhongfeng Wang, Qinghong Shen, Hongbing Pan:
A Novel Approximation Methodology and Its Efficient VLSI Implementation for the Sigmoid Function. IEEE Trans. Circuits Syst. 67-II(12): 3422-3426 (2020) - [j70]Yuxuan Wang, Yuanyong Luo, Zhongfeng Wang, Qinghong Shen, Hongbing Pan:
GH CORDIC-Based Architecture for Computing $N$ th Root of Single-Precision Floating-Point Number. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 864-875 (2020) - [j69]Wendong Mao, Jun Lin, Zhongfeng Wang:
F-DNA: Fast Convolution Architecture for Deconvolutional Network Acceleration. IEEE Trans. Very Large Scale Integr. Syst. 28(8): 1867-1880 (2020) - [j68]Hangxuan Cui, Jun Lin, Zhongfeng Wang:
Information Storage Bit-Flipping Decoder for LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2464-2468 (2020) - [c130]Liulu He, Xiaoru Xie, Jun Lin, Zhongfeng Wang:
Efficient FPGA design for Convolutions in CNN based on FFT-pruning. APCCAS 2020: 27-30 - [c129]Danyang Zhu, Yifeng Song, Jing Tian, Zhongfeng Wang, Haobo Yu:
An Efficient Accelerator of the Squaring for the Verifiable Delay Function Over a Class Group. APCCAS 2020: 137-140 - [c128]Xiao Hu, Jing Tian, Zhongfeng Wang:
Fast Permutation Architecture on Encrypted Data for Secure Neural Network Inference. APCCAS 2020: 141-144 - [c127]Jiayu Wen, Yufei Ma, Zhongfeng Wang:
An Efficient FPGA Accelerator Optimized for High Throughput Sparse CNN Inference. APCCAS 2020: 165-168 - [c126]Chao Ni, Jinming Lu, Jun Lin, Zhongfeng Wang:
LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks. APCCAS 2020: 201-204 - [c125]Yufei Ma, Yuan Du, Li Du, Jun Lin, Zhongfeng Wang:
In-Memory Computing: The Next-Generation AI Computing Paradigm. ACM Great Lakes Symposium on VLSI 2020: 265-270 - [c124]Zhiyuan Chen, Yufei Ma, Zhongfeng Wang:
Optimizing Stochastic Computing for Low Latency Inference of Convolutional Neural Networks. ICCAD 2020: 90:1-90:7 - [c123]Binjing Li, Keli Xie, Siyuan Lu, Jun Lin, Zhongfeng Wang:
LSTM-Based Quantitative Trading Using Dynamic K-Top and Kelly Criterion. IJCNN 2020: 1-8 - [c122]Shuang Liang, Siyuan Lu, Jun Lin, Zhongfeng Wang:
Hardware Accelerator for Engle-Granger Cointegration in Pairs Trading. ISCAS 2020: 1-5 - [c121]Manzhen Wang, Yuanyong Luo, Mengyu An, Yuou Qiu, Muhan Zheng, Zhongfeng Wang, Hongbing Pan:
An Optimized Compression Strategy for Compressor-Based Approximate Multiplier. ISCAS 2020: 1-5 - [c120]Yujie Zhang, Jiajun Wu, Minghao Li, Jun Lin, Zhongfeng Wang:
A Three-Level Scoring System for Fast Similarity Evaluation Based on Smith-Waterman Algorithm. ISCAS 2020: 1-5 - [c119]Chenhui Feng, Hui Qian, Zhongfeng Wang:
An Implementation of Pre-Quantized Random Demodulator Based on Amplitude-to-Pulse Converter. ISVLSI 2020: 206-211 - [c118]Bo Wu, Jing Tian, Xiao Hu, Zhongfeng Wang:
A Novel Modular Multiplier for Isogeny-Based Post-Quantum Cryptography. ISVLSI 2020: 334-339 - [c117]Hui Zhang, Wei Wu, Yufei Ma, Zhongfeng Wang:
Efficient Hardware Post Processing of Anchor-Based Object Detection on FPGA. ISVLSI 2020: 580-585 - [c116]Jing Zeng, Jun Lin, Zhongfeng Wang:
A Serial Maximum-likelihood Detection Algorithm for Massive MIMO Systems. NEWCAS 2020: 78-81 - [c115]Peixiang Yang, Wendong Mao, Jun Lin, Zhongfeng Wang:
A Computation-Efficient Solution for Acceleration of Generative Adversarial Network. NEWCAS 2020: 210-213 - [c114]Meiqi Wang, Ruixin Xue, Jun Lin, Zhongfeng Wang:
Exploring Quantization in Few-Shot Learning. NEWCAS 2020: 279-282 - [c113]Binjing Li, Fenggui Liu, Jun Lin, Zhongfeng Wang:
Financial Time Series Forecasting Model Based on EMD and Rolling Grey Model. SiPS 2020: 1-6 - [c112]Jinming Lu, Jun Lin, Zhongfeng Wang:
A Reconfigurable DNN Training Accelerator on FPGA. SiPS 2020: 1-6 - [c111]Haonan Wang, Yuchen Mei, Jun Lin, Zhongfeng Wang:
Temporal Residual Feature Learning for Efficient 3D Convolutional Neural Network on Action Recognition Task. SiPS 2020: 1-6 - [c110]Yuchen Mei, Li Du, Xuewen He, Yuan Du, Xiaoliang Chen, Zhongfeng Wang:
A Reconfigurable Permutation Based Address Encryption Architecture for Memory Security. SoCC 2020: 7-12 - [c109]Siyuan Lu, Meiqi Wang, Shuang Liang, Jun Lin, Zhongfeng Wang:
Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer. SoCC 2020: 84-89 - [c108]Yifeng Song, Danyang Zhu, Jing Tian, Zhongfeng Wang:
A High-Speed Architecture for the Reduction in VDF Based on a Class Group. SoCC 2020: 147-152 - [c107]Xiao Wu, Yufei Ma, Zhongfeng Wang:
Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGA. SoCC 2020: 168-173 - [c106]Shouliang Guo, Chao Fang, Jun Lin, Zhongfeng Wang:
A Configurable FPGA Accelerator of Bi-LSTM Inference with Structured Sparsity. SoCC 2020: 174-179 - [i10]Siyuan Lu, Meiqi Wang, Shuang Liang, Jun Lin, Zhongfeng Wang:
Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer. CoRR abs/2009.08605 (2020) - [i9]Jing Tian, Jun Lin, Zhongfeng Wang:
Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. 2020: 246 (2020) - [i8]Jing Tian, Piaoyang Wang, Zhe Liu, Jun Lin, Zhongfeng Wang, Johann Großschädl:
Faster Software Implementation of the SIKE Protocol Based on A New Data Representation. IACR Cryptol. ePrint Arch. 2020: 660 (2020) - [i7]Jing Tian, Bo Wu, Zhongfeng Wang:
High-Speed FPGA Implementation of the SIKE Based on An Ultra-Low-Latency Modular Multiplier. IACR Cryptol. ePrint Arch. 2020: 1125 (2020)
2010 – 2019
- 2019
- [j67]Xingcheng Liu, Li'e Zi, Dong Yang, Zhongfeng Wang:
Improved Decoding Algorithms of LDPC Codes Based on Reliability Metrics of Variable Nodes. IEEE Access 7: 35769-35778 (2019) - [j66]Jing Tian, Suwen Song, Jun Lin, Zhongfeng Wang:
Efficient T-EMS Based Decoding Algorithms for High-Order LDPC Codes. IEEE Access 7: 50980-50992 (2019) - [j65]Siyuan Lu, Jinming Lu, Jun Lin, Zhongfeng Wang:
A Hardware-Oriented and Memory-Efficient Method for CTC Decoding. IEEE Access 7: 120681-120694 (2019) - [j64]Meiqi Wang, Zhisheng Wang, Jinming Lu, Jun Lin, Zhongfeng Wang:
E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(2): 280-291 (2019) - [j63]Wenjie Li, Jing Tian, Jun Lin, Zhongfeng Wang:
Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders. IEEE Commun. Lett. 23(5): 785-788 (2019) - [j62]Yangcan Zhou, Jun Lin, Zhongfeng Wang:
Improved Fast-SSC-Flip Decoding of Polar Codes. IEEE Commun. Lett. 23(6): 950-953 (2019) - [j61]Yongsheng Yin, Liu Liu, Hongmei Chen, Honghui Deng, Xu Meng, Jing-Sheng Wu, Zhongfeng Wang:
A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs. IEICE Electron. Express 16(19): 20190540 (2019) - [j60]Yizhi Wang, Jun Lin, Zhongfeng Wang:
FPAP: A Folded Architecture for Energy-Quality Scalable Convolutional Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 288-301 (2019) - [j59]Yangcan Zhou, Zhiyu Chen, Jun Lin, Zhongfeng Wang:
A High-Speed Successive-Cancellation Decoder for Polar Codes Using Approximate Computing. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 227-231 (2019) - [j58]Congyi Zhu, Jun Lin, Zhongfeng Wang:
A New Clock Phase Calibration Method in High-Speed and High-Resolution DACs. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 332-336 (2019) - [j57]Congyi Zhu, Jun Lin, Zhongfeng Wang:
Background Calibration of Comparator Offsets in SHA-Less Pipelined ADCs. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 357-361 (2019) - [j56]Hangxuan Cui, Jun Lin, Zhongfeng Wang:
An Efficient Post-Processor for Lowering the Error Floor of LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 397-401 (2019) - [j55]Wenjie Li, Jun Lin, Zhongfeng Wang:
A 124-Gb/s Decoder for Generalized Integrated Interleaved Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 3174-3187 (2019) - [j54]Hangxuan Cui, Jun Lin, Zhongfeng Wang:
An Improved Gradient Descent Bit-Flipping Decoder for LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 3188-3200 (2019) - [j53]Congyi Zhu, Renrong Liang, Jun Lin, Zhongfeng Wang, Li Li:
Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2008-2020 (2019) - [j52]Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan:
Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2156-2169 (2019) - [j51]Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan:
Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base". IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2222 (2019) - [c105]Hangxuan Cui, Khoa LeTrung, Fakhreddine Ghaffari, David Declercq, Jun Lin, Zhongfeng Wang:
An Enhanced Offset Min-Sum decoder for 5G LDPC Codes. APCC 2019: 490-495 - [c104]Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang:
Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes. ASICON 2019: 1-4 - [c103]Haonan Wang, Wenjian Liu, Tianyi Xu, Jun Lin, Zhongfeng Wang:
A Low-latency Sparse-Winograd Accelerator for Convolutional Neural Networks. ICASSP 2019: 1448-1452 - [c102]Yangcan Zhou, Jun Lin, Zhongfeng Wang:
A New Fast-SSC-Flip Decoding of Polar Codes. ICC 2019: 1-6 - [c101]Chunhua Deng, Fangxuan Sun, Xuehai Qian, Jun Lin, Zhongfeng Wang, Bo Yuan:
TIE: energy-efficient tensor train-based inference engine for deep neural network. ISCA 2019: 264-278 - [c100]Hangxuan Cui, Jun Lin, Suwen Song, Zhongfeng Wang:
A New Probabilistic Gradient Descent Bit Flipping Decoder for LDPC Codes. ISCAS 2019: 1-5 - [c99]Wenjian Liu, Jun Lin, Zhongfeng Wang:
USCA: A Unified Systolic Convolution Array Architecture for Accelerating Sparse Neural Network. ISCAS 2019: 1-5 - [c98]Wendong Mao, Jichen Wang, Jun Lin, Zhongfeng Wang:
Methodology for Efficient Reconfigurable Architecture of Generative Neural Network. ISCAS 2019: 1-5 - [c97]Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang:
A Novel Low-Complexity Joint Coding and Decoding Algorithm for NB-LDPC Codes. ISCAS 2019: 1-5 - [c96]Hangxuan Cui, Khoa Le, Fakhreddine Ghaffari, David Declercq, Jun Lin, Zhongfeng Wang:
A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes. ISCIT 2019: 616-620 - [c95]Xiaoru Xie, Fangxuan Sun, Jun Lin, Zhongfeng Wang:
Fast-ABC: A Fast Architecture for Bottleneck-Like Based Convolutional Neural Networks. ISVLSI 2019: 1-6 - [c94]Zengchao Yan, Jun Lin, Zhongfeng Wang:
A Low-Complexity RS Decoder for Triple-Error-Correcting RS Codes. ISVLSI 2019: 489-494 - [c93]Jing Zeng, Yangcan Zhou, Jun Lin, Zhongfeng Wang:
Hardware Implementation of Improved Fast-SSC-Flip Decoder for Polar Codes. ISVLSI 2019: 580-585 - [c92]Zengchao Yan, Wenjie Li, Jun Lin, Zhongfeng Wang:
A Low-Complexity Error-and-Erasure Decoding Algorithm for t=2 RS Codes. SiPS 2019: 43-47 - [c91]Chao Chen, Yunghsiang S. Han, Zhongfeng Wang, Baoming Bai:
A New Inversionless Berlekamp-Massey Algorithm with Efficient Architecture. SiPS 2019: 48-53 - [c90]Yuanyong Luo, Hongbing Pan, Qinghong Shen, Zhongfeng Wang:
CLA Formula Aided Fast Architecture Design for Clustered Look-Ahead Pipelined IIR Digital Filter. SiPS 2019: 60-66 - [c89]Wenjian Liu, Xiayuan Wen, Jun Lin, Zhongfeng Wang, Li Du:
EAGLE: Exploiting Essential Address in Both Weight and Activation to Accelerate CNN Computing. SiPS 2019: 73-78 - [c88]Jing Tian, Jun Lin, Zhongfeng Wang:
Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography. SiPS 2019: 97-102 - [c87]Meiqi Wang, Jianqiao Mo, Jun Lin, Zhongfeng Wang, Li Du:
DynExit: A Dynamic Early-Exit Strategy for Deep Residual Networks. SiPS 2019: 178-183 - [c86]Jing Zeng, Jun Lin, Zhongfeng Wang, Yun Chen:
Hybrid Preconditioned CG Detection with Sequential Update for Massive MIMO Systems. SiPS 2019: 207-212 - [c85]Siyuan Lu, Jinming Lu, Jun Lin, Zhongfeng Wang, Li Du:
A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding. SiPS 2019: 352-357 - [c84]Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Lin, Zhongfeng Wang, Li Du:
Training Deep Neural Networks Using Posit Number System. SoCC 2019: 62-67 - [i6]Siyuan Lu, Jinming Lu, Jun Lin, Zhongfeng Wang:
A Hardware-Oriented and Memory-Efficient Method for CTC Decoding. CoRR abs/1905.03175 (2019) - [i5]Haonan Wang, Jun Lin, Zhongfeng Wang:
Design Light-weight 3D Convolutional Networks for Video Recognition Temporal Residual, Fully Separable Block, and Fast Algorithm. CoRR abs/1905.13388 (2019) - [i4]Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Lin, Zhongfeng Wang, Li Du:
Training Deep Neural Networks Using Posit Number System. CoRR abs/1909.03831 (2019) - [i3]Jing Tian, Zhe Liu, Jun Lin, Zhongfeng Wang, Binjing Li:
High-Speed Modular Multipliers for Isogeny-Based Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. 2019: 1206 (2019) - 2018
- [j50]Dingheng Chen, Yinshui Xia, Zhongfeng Wang:
Stuck-at-close defect propagation and its blocking technique in CMOL cell mapping. Microelectron. J. 72: 100-108 (2018) - [j49]Zhisheng Wang, Jun Lin, Zhongfeng Wang:
Hardware-Oriented Compression of Long Short-Term Memory for Efficient Inference. IEEE Signal Process. Lett. 25(7): 984-988 (2018) - [j48]Jing Tian, Jun Lin, Zhongfeng Wang:
A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications. IEEE Trans. Circuits Syst. II Express Briefs 65-II(2): 226-230 (2018) - [j47]Jichen Wang, Jun Lin, Zhongfeng Wang:
Efficient Hardware Architectures for Deep Convolutional Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1941-1953 (2018) - [j46]Jing Zeng, Jun Lin, Zhongfeng Wang:
An Improved Gauss-Seidel Algorithm and Its Efficient Architecture for Massive MIMO Systems. IEEE Trans. Circuits Syst. II Express Briefs 65-II(9): 1194-1198 (2018) - [j45]Yuanyong Luo, Yuxuan Wang, Huaqing Sun, Yi Zha, Zhongfeng Wang, Hongbing Pan:
CORDIC-Based Architecture for Computing Nth Root and Its Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4183-4195 (2018) - [j44]Xingcheng Liu, Feng Xiong, Zhongfeng Wang, Shuo Liang:
Design of Binary LDPC Codes With Parallel Vector Message Passing. IEEE Trans. Commun. 66(4): 1363-1375 (2018) - [j43]Yizhi Wang, Jun Lin, Zhongfeng Wang:
An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 280-293 (2018) - [j42]Jin Sha, Jingbo Liu, Jun Lin, Zhongfeng Wang:
A Stage-Combined Belief Propagation Decoder for Polar Codes. J. Signal Process. Syst. 90(5): 687-694 (2018) - [j41]Jing Zeng, Jun Lin, Zhongfeng Wang:
Low Complexity Message Passing Detection Algorithm for Large-Scale MIMO Systems. IEEE Wirel. Commun. Lett. 7(5): 708-711 (2018) - [c83]Haonan Wang, Jun Lin, Yi Xie, Bo Yuan, Zhongfeng Wang:
Efficient Reconfigurable Hardware Core for Convolutional Neural Networks. ACSSC 2018: 777-781 - [c82]Zengchao Yan, Wenjie Li, Jun Lin, Zhongfeng Wang:
Fast and Low-Complexity Decoding Algorithm and Architecture for Quadruple-Error-Correcting RS codes. APCCAS 2018: 191-194 - [c81]Meiqi Wang, Siyuan Lu, Danyang Zhu, Jun Lin, Zhongfeng Wang:
A High-Speed and Low-Complexity Architecture for Softmax Function in Deep Learning. APCCAS 2018: 223-226 - [c80]Jing Tian, Jun Lin, Zhongfeng Wang:
Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-LDPC Decoding. APCCAS 2018: 227-230 - [c79]Xin Jin, Jun Lin, Zhongfeng Wang:
A Novel Compiler for Regular Expression Matching Engine Construction. APCCAS 2018: 251-256 - [c78]Chenxi Lin, Hui Qian, Zhongfeng Wang:
A High-Throughout Real-Time Prewitt Operator on Embedded NEON+ARM System. APCCAS 2018: 270-273 - [c77]Fangxuan Sun, Jun Lin, Zhongfeng Wang:
Eadnet: Efficient Architecture for Decomposed Convolutional Neural Networks. ICASSP 2018: 1145-1149 - [c76]Jing Tian, Jun Lin, Zhongfeng Wang:
An Efficient NB-LDPC Decoding Algorithm for Next-Generation Memories. ISCAS 2018: 1-5 - [c75]Yaqi Wang, Jun Lin, Zhongfeng Wang:
A New Soft-input Hard-output decoding algorithm for Turbo Product Codes. ISCAS 2018: 1-5 - [c74]Yizhi Wang, Jun Lin, Zhongfeng Wang:
An Efficient Convolution Core Architecture for Privacy-Preserving Deep Learning. ISCAS 2018: 1-5 - [c73]Yizhi Wang, Jun Lin, Zhongfeng Wang:
FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks. ISVLSI 2018: 503-508 - [c72]Fangxuan Sun, Jun Lin, Zhongfeng Wang:
An Optimized Architecture For Decomposed Convolutional Neural Networks. ISVLSI 2018: 516-521 - [c71]Jichen Wang, Jun Lin, Zhongfeng Wang:
Bandwidth Efficient Architectures for Convolutional Neural Network. SiPS 2018: 94-99 - [c70]Yangcan Zhou, Jun Lin, Jichen Wang, Zhongfeng Wang:
Approximate Comparator: Design and Analysis. SiPS 2018: 129-133 - [i2]Zhisheng Wang, Fangxuan Sun, Jun Lin, Zhongfeng Wang, Bo Yuan:
SGAD: Soft-Guided Adaptively-Dropped Neural Network. CoRR abs/1807.01430 (2018) - 2017
- [j40]Tongtong Wang, Zhongfeng Wang, Xinyuan Wang, Junqing Sun, Ali Ghiasi:
Analysis and Comparison of FEC Schemes for 200GbE and 400GbE. IEEE Commun. Stand. Mag. 1(1): 24-30 (2017) - [j39]Chuan Zhang, Yuan-Hao Huang, Farhana Sheikh, Zhongfeng Wang:
Guest Editorial Advanced Baseband Processing Circuits and Systems for 5G Communications. IEEE J. Emerg. Sel. Topics Circuits Syst. 7(4): 473-476 (2017) - [j38]Chuan Zhang, Yuan-Hao Huang, Farhana Sheikh, Zhongfeng Wang:
Advanced Baseband Processing Algorithms, Circuits, and Implementations for 5G Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. 7(4): 477-490 (2017) - [j37]Jun Zhou, Amir Tofighi Zavareh, Robin Gupta, Liang Liu, Zhongfeng Wang, Brian M. Sadler, José Silva-Martínez, Sebastian Hoyos:
Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2495-2507 (2017) - [j36]Yi Xie, Siyu Liao, Bo Yuan, Yanzhi Wang, Zhongfeng Wang:
Fully-Parallel Area-Efficient Deep Neural Network Design Using Stochastic Computing. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12): 1382-1386 (2017) - [j35]Xian Wei, Yuanxiang Li, Hao Shen, Fang Chen, Martin Kleinsteuber, Zhongfeng Wang:
Dynamical Textures Modeling via Joint Video Dictionary Learning. IEEE Trans. Image Process. 26(6): 2929-2943 (2017) - [j34]Jun Lin, Zhiyuan Yan, Zhongfeng Wang:
Efficient Soft Cancelation Decoder Architectures for Polar Codes. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 87-99 (2017) - [j33]Guanghui Hu, Jin Sha, Zhongfeng Wang:
High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1159-1163 (2017) - [j32]Zhisheng Wang, Jun Lin, Zhongfeng Wang:
Accelerating Recurrent Neural Networks: A Memory-Efficient Approach. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2763-2775 (2017) - [c69]Xiao Liang, Huayi Zhou, Zhongfeng Wang, Xiaohu You, Chuan Zhang:
Segmented successive cancellation list polar decoding with joint BCH-CRC codes. ACSSC 2017: 1509-1513 - [c68]Weihong Xu, Zhongfeng Wang, Xiaohu You, Chuan Zhang:
Efficient fast convolution architectures for convolutional neural network. ASICON 2017: 904-907 - [c67]Yangcan Zhou, Jun Lin, Zhongfeng Wang:
Energy efficient SVM classifier using approximate computing. ASICON 2017: 1045-1048 - [c66]Shusen Jing, Junmei Yang, Zhongfeng Wang, Xiaohu You, Chuan Zhang:
Algorithm and architecture for joint detection and decoding for MIMO with LDPC codes. ISCAS 2017: 1-4 - [c65]Yangcan Zhou, Jun Lin, Zhongfeng Wang:
Efficient approximate layered LDPC decoder. ISCAS 2017: 1-4 - [c64]Haijian Wu, Jun Lin, Chuan Zhang, Zhongfeng Wang:
Low-complexity detection algorithms based on matrix partition for massive MIMO. WCSP 2017: 1-6 - [c63]Haochuan Zhu, Jun Lin, Zhongfeng Wang:
Reduced complexity message passing detection algorithm in large-scale MIMO systems. WCSP 2017: 1-5 - 2016
- [j31]Kai Huang, Jin Sha, Wei Shi, Zhongfeng Wang:
An Efficient FPGA Implementation for 2-D MUSIC Algorithm. Circuits Syst. Signal Process. 35(5): 1795-1805 (2016) - [j30]Bo Yuan, Yanzhi Wang, Zhongfeng Wang:
Area-Efficient Scaling-Free DFT/FFT Design Using Stochastic Computing. IEEE Trans. Circuits Syst. II Express Briefs 63-II(12): 1131-1135 (2016) - [c62]Bo Yuan, Yanzhi Wang, Zhongfeng Wang:
Area-Efficient Error-Resilient Discrete Fourier Transformation Design using Stochastic Computing. ACM Great Lakes Symposium on VLSI 2016: 33-38 - [c61]Bo Yuan, Chuan Zhang, Zhongfeng Wang:
Design space exploration for hardware-efficient stochastic computing: A case study on discrete cosine transformation. ICASSP 2016: 6555-6559 - [c60]Jun Lin, Jin Sha, Li Li, Chenrong Xiong, Zhiyuan Yan, Zhongfeng Wang:
A high throughput belief propagation decoder architecture for polar codes. ISCAS 2016: 153-156 - [c59]Jin Sha, Jun Lin, Zhongfeng Wang:
Stage-combined belief propagation decoding of polar codes. ISCAS 2016: 421-424 - [c58]Bo Yuan, Yanzhi Wang, Zhongfeng Wang:
Area-efficient scaling-free DFT/FFT design using stochastic computing. ISCAS 2016: 2904 - [c57]Jun Zhou, Zhongfeng Wang, Sebastian Hoyos:
Compressed Power Spectral Density Estimation via Group-Based Total Variation Minimization. SiPS 2016: 7-10 - [c56]Guanghui Hu, Jin Sha, Zhongfeng Wang:
Beyond 100Gbps Encoder Design for Staircase Codes. SiPS 2016: 154-158 - [c55]Zhisheng Wang, Jun Lin, Zhongfeng Wang:
An Efficient Hardware Architecture for Lossless Data Compression in Data Center. SiPS 2016: 159-164 - [c54]Fangxuan Sun, Jun Lin, Zhongfeng Wang:
Intra-layer nonuniform quantization of convolutional neural network. WCSP 2016: 1-5 - [c53]Jichen Wang, Jun Lin, Zhongfeng Wang:
Efficient convolution architectures for convolutional neural network. WCSP 2016: 1-5 - 2015
- [c52]Xing Liu, Jin Sha, Chuan Zhang, Zhongfeng Wang:
A stage-reduced low-latency successive cancellation decoder for polar codes. DSP 2015: 258-262 - 2014
- [j29]Chuan Zhang, Zhongfeng Wang, Xiaohu You:
Efficient Decoder Architecture for Single Block-Row Quasi-Cyclic LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 61-II(10): 793-797 (2014) - [c51]Chuan Zhang, Zhongfeng Wang, Xiaohu You, Bo Yuan:
Efficient adaptive list successive cancellation decoder for polar codes. ACSSC 2014: 126-130 - [c50]Chuan Zhang, Shenghui Weng, Xiaohu You, Zhongfeng Wang:
Area-efficient check node unit architecture for single block-row quasi-cyclic LDPC codes. APCCAS 2014: 431-434 - [c49]Zhiqiang Cui, Zhongfeng Wang, Xinming Huang:
Multilevel error correction scheme for MLC flash memory. ISCAS 2014: 201-204 - [c48]Leixin Zhou, Jin Sha, Yun Chen, Chuan Zhang, Zhongfeng Wang:
Efficient symbol reliability based decoding for QCNB-LDPC codes. ISCAS 2014: 405-408 - [c47]Chuan Zhang, Xiaohu You, Zhongfeng Wang:
Efficient column-layered decoders for single block-row quasi-cyclic LDPC codes. ISCAS 2014: 413-416 - 2013
- [c46]Leixin Zhou, Jin Sha, Yun Chen, Zhongfeng Wang:
Memory efficient EMS decoding for non-binary LDPC codes. ISCAS 2013: 1336-1339 - 2012
- [j28]Kai He, Jin Sha, Zhongfeng Wang:
Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing. IEEE Trans. Circuits Syst. II Express Briefs 59-II(6): 381-385 (2012) - [j27]Jinjin He, Huaping Liu, Zhongfeng Wang, Xinming Huang, Kai Zhang:
High-Speed Low-Power Viterbi Decoder Design for TCM Decoders. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 755-759 (2012) - [j26]Li Li, Bo Yuan, Zhongfeng Wang, Jin Sha, Hongbing Pan, Weishan Zheng:
Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction. IEEE Trans. Very Large Scale Integr. Syst. 20(7): 1346-1350 (2012) - [c45]Kai He, Jin Sha, Zhongfeng Wang:
Memory efficient column-layered decoder design for non-binary LDPC codes. ISCAS 2012: 2613-2616 - [c44]Leixin Zhou, Jin Sha, Zhongfeng Wang:
Efficient EMS decoding for non-binary LDPC codes. ISOCC 2012: 339-342 - [i1]Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang:
Reduced-Complexity Column-Layered Decoding and Implementation for LDPC Codes. CoRR abs/1204.2577 (2012) - 2011
- [j25]Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang:
Reduced-complexity column-layered decoding and implementation for LDPC codes. IET Commun. 5(15): 2177-2186 (2011) - [j24]Kai Zhang, Xinming Huang, Zhongfeng Wang:
A High-Throughput LDPC Decoder Architecture With Rate Compatibility. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(4): 839-847 (2011) - [c43]Kai He, Jin Sha, Zhongfeng Wang:
Memory efficient decoder design of nonbinary LDPC codes. ISOCC 2011: 44-47 - 2010
- [j23]Jun Lin, Jin Sha, Zhongfeng Wang, Li Li:
An Efficient VLSI Architecture for Nonbinary LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs 57-II(1): 51-55 (2010) - [j22]Chuan Zhang, Zhongfeng Wang, Jin Sha, Li Li, Jun Lin:
Flexible LDPC Decoder Design for Multigigabit-per-Second Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 116-124 (2010) - [j21]Jun Lin, Jin Sha, Zhongfeng Wang, Li Li:
Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(5): 1071-1082 (2010) - [j20]Kai Zhang, Xinming Huang, Zhongfeng Wang:
A dual-rate LDPC decoder for china multimedia mobile broadcasting systems. IEEE Trans. Consumer Electron. 56(2): 399-407 (2010) - [c42]Shuai Zhou, Jin Sha, Li Li, Zhongfeng Wang:
Layered decoding for non-binary LDPC codes. ISCAS 2010: 481-484 - [c41]Kai He, Jin Sha, Li Li, Zhongfeng Wang:
Low power decoder design for QC-LDPC codes. ISCAS 2010: 3937-3940
2000 – 2009
- 2009
- [j19]Kai Zhang, Xinming Huang, Zhongfeng Wang:
High-throughput layered decoder implementation for quasi-cyclic LDPC codes. IEEE J. Sel. Areas Commun. 27(6): 985-994 (2009) - [j18]Jun Lin, Zhongfeng Wang, Li Li, Jin Sha, Minglun Gao:
Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs 56-II(3): 215-219 (2009) - [j17]Bo Yuan, Zhongfeng Wang, Li Li, Minglun Gao, Jin Sha, Chuan Zhang:
Area-efficient reed-solomon decoder design for optical communications. IEEE Trans. Circuits Syst. II Express Briefs 56-II(6): 469-473 (2009) - [j16]Jin Sha, Jun Lin, Zhongfeng Wang, Li Li, Minglun Gao:
Decoder Design for RS-Based LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 56-II(9): 724-728 (2009) - [j15]Jin Sha, Jun Lin, Zhongfeng Wang, Li Li, Minglun Gao:
LDPC decoder design for high rate wireless personal area networks. IEEE Trans. Consumer Electron. 55(2): 455-460 (2009) - [j14]Zhigang Wu, Jin Sha, Zhongfeng Wang, Li Li, Minglun Gao:
An improved scaled DCT architecture. IEEE Trans. Consumer Electron. 55(2): 685-689 (2009) - [j13]Jin Sha, Zhongfeng Wang, Minglun Gao, Li Li:
Multi-Gb/s LDPC Code Design and Implementation. IEEE Trans. Very Large Scale Integr. Syst. 17(2): 262-268 (2009) - [j12]Zhiqiang Cui, Zhongfeng Wang, Youjian Liu:
High-Throughput Layered LDPC Decoding Architecture. IEEE Trans. Very Large Scale Integr. Syst. 17(4): 582-587 (2009) - [c40]Kai Zhang, Xinming Huang, Zhongfeng Wang:
An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB Systems. ASAP 2009: 235-238 - [c39]Chuan Zhang, Li Li, Jun Xu, Zhongfeng Wang:
High-throughput GCM VLSI Architecture for IEEE 802.1ae Applications. ISCAS 2009: 900-903 - [c38]Jin Sha, Jun Lin, Li Li, Minglun Gao, Zhongfeng Wang:
LDPC Decoder Design for IEEE 802.15 Standard. ISCAS 2009: 2441-2444 - [c37]Bo Yuan, Li Li, Jin Sha, Zhongfeng Wang:
Area-efficient Reed-Solomon Decoder Design for 10-100 Gb/s Applications. ISCAS 2009: 2681-2684 - [c36]Jinjin He, Zhongfeng Wang, Zhiqiang Cui, Li Li:
Towards an Optimal Trade-off of Viterbi Decoder Design. ISCAS 2009: 3030-3033 - [c35]Bo Yuan, Li Li, Zhongfeng Wang:
High-speed area-efficient versatile Reed-Solomon decoder design for multi-mode applications. SiPS 2009: 179-184 - [c34]Jun Lin, Jin Sha, Zhongfeng Wang, Li Li:
An improved min-sum based column-layered decoding algorithm for LDPC codes. SiPS 2009: 238-242 - 2008
- [j11]Zhiqiang Cui, Zhongfeng Wang:
Improved low-complexity low-density parity-check decoding. IET Commun. 2(8): 1061-1068 (2008) - [c33]Qingwei Li, Zhongfeng Wang, Xingcheng Liu:
Fast point operation architecture for Elliptic Curve Cryptography. APCCAS 2008: 184-188 - [c32]Qingwei Li, Zhongfeng Wang, Xingcheng Liu:
Efficient radius and list updating units design for list sphere decoders. APCCAS 2008: 1098-1102 - [c31]Qingwei Li, Zhongfeng Wang, Xinmiao Zhang, Xingcheng Liu:
Efficient architecture for the Tate pairing in characteristic three. APCCAS 2008: 1111-1115 - [c30]Chuan Zhang, Li Li, Jun Lin, Zhongfeng Wang:
Low-complexity shift-LDPC decoder for high-speed communication systems. APCCAS 2008: 1636-1639 - [c29]Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang, Qingwei Jia:
Efficient decoder design for high-throughput LDPC decoding. APCCAS 2008: 1640-1643 - [c28]Zhiqiang Cui, Zhongfeng Wang:
Extended layered decoding of LDPC codes. ACM Great Lakes Symposium on VLSI 2008: 457-462 - [c27]Jinjin He, Jian Cui, Lianxing Yang, Zhongfeng Wang:
A low-complexity high-performance noncoherent receiver for GFSK signals. ISCAS 2008: 1256-1259 - [c26]Jinjin He, Zhongfeng Wang, Huaping Liu:
Low-complexity high-speed 4-D TCM decoder. SiPS 2008: 216-220 - 2007
- [j10]Zhongfeng Wang, Qingwei Li:
Very Low-Complexity Hardware Interleaver for Turbo Decoding. IEEE Trans. Circuits Syst. II Express Briefs 54-II(7): 636-640 (2007) - [j9]Zhongfeng Wang, Zhiqiang Cui:
Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 15(1): 104-114 (2007) - [j8]Zhongfeng Wang:
High-Speed Recursion Architectures for MAP-Based Turbo Decoders. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 470-474 (2007) - [j7]Zhongfeng Wang, Zhiqiang Cui:
A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 483-488 (2007) - [j6]Jun Ma, Alexander Vardy, Zhongfeng Wang:
Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. Very Large Scale Integr. Syst. 15(11): 1225-1238 (2007) - [c25]Jun Ma, Alexander Vardy, Zhongfeng Wang, Qinqin Chen:
Factorization Architecture by Direct Root Computation for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. ICASSP (2) 2007: 1-4 - [c24]Zhiqiang Cui, Zhongfeng Wang:
Efficient Message Passing Architecture for High Throughput LDPC Decoder. ISCAS 2007: 917-920 - [c23]Jun Ma, Alexander Vardy, Zhongfeng Wang, Qinqin Chen:
Direct Root Computation Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. ISCAS 2007: 1409-1412 - [c22]Qinqin Chen, Zhongfeng Wang, Jun Ma:
FPGA Implementation of an Interpolation Processor for Soft-Decision Decoding of Reed-Solomon Codes. ISCAS 2007: 2100-2103 - [c21]Qingwei Li, Zhongfeng Wang:
Early-Pruning K-Best Sphere Decoder for MIMO Systems. SiPS 2007: 40-44 - [c20]Lupin Chen, Jinjin He, Zhongfeng Wang:
Design of Low-Power Memory-Efficient Viterbi Decoder. SiPS 2007: 132-135 - [c19]Zhiqiang Cui, Zhongfeng Wang:
Studies on Practical Low Complexity Decoding of Low-Density Parity-Check Codes. SiPS 2007: 216-221 - [c18]Somya Rathi, Zhongfeng Wang:
Fast EBCOT Encoder Architecture for JPEG 2000. SiPS 2007: 595-599 - 2006
- [j5]Zhongfeng Wang, Jun Ma:
High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. Very Large Scale Integr. Syst. 14(9): 937-950 (2006) - [c17]Jin Sha, Minglun Gao, Zhongjin Zhang, Li Li, Zhongfeng Wang:
An FPGA Implementation of Array LDPC Decoder. APCCAS 2006: 1675-1678 - [c16]Zhongfeng Wang, Yuping Zhang, Keshab K. Parhi:
Study of Early Stopping Criteria for Turbo Decoding and Their Applications in WCDMA Systems. ICASSP (3) 2006: 1016-1019 - [c15]Zhiqiang Cui, Zhongfeng Wang:
A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA. ISCAS 2006 - [c14]Zhiqiang Cui, Zhongfeng Wang:
Area-efficient parallel decoder architecture for high rate QC-LDPC codes. ISCAS 2006 - [c13]Qingwei Li, Zhongfeng Wang:
Improved k-best sphere decoding algorithms for MIMO systems. ISCAS 2006 - [c12]Jun Ma, Alexander Vardy, Zhongfeng Wang:
Reencoder design for soft-decision decoding of an (255, 239) Reed-Solomon code. ISCAS 2006 - [c11]Jun Ma, Alexander Vardy, Zhongfeng Wang:
Efficient fast interpolation architecture for soft-decision decoding of Reed-Solomon codes. ISCAS 2006 - 2004
- [j4]Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi:
On the better protection of short-frame turbo codes. IEEE Trans. Commun. 52(9): 1435-1439 (2004) - [c10]Zhongfeng Wang, Yanni Chen, Keshab K. Parhi:
Area efficient decoding of quasi-cyclic low density parity check codes. ICASSP (5) 2004: 49-52 - 2003
- [j3]Zhongfeng Wang, Keshab K. Parhi:
High performance, high throughput turbo/SOVA decoder design. IEEE Trans. Commun. 51(4): 570-579 (2003) - [c9]Zhongfeng Wang, Keshab K. Parhi:
Efficient interleaver memory architectures for serial turbo decoding. ICASSP (2) 2003: 629-632 - 2002
- [j2]Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi:
Area-efficient high-speed decoding schemes for turbo decoders. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 902-912 (2002) - 2001
- [j1]Zhongfeng Wang, Hiroshi Suzuki, Keshab K. Parhi:
Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders. J. VLSI Signal Process. 29(3): 209-221 (2001) - [c8]Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi:
Area-efficient high speed decoding schemes for turbo/MAP decoders. ICASSP 2001: 2633-2636 - [c7]Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi:
A study on the performance, power consumption tradeoffs of short frame turbo decoder design. ICASSP 2001: 2637-2640 - [c6]Tong Zhang, Zhongfeng Wang, Keshab K. Parhi:
On finite precision implementation of low density parity check codes decoder. ISCAS (4) 2001: 202-205 - 2000
- [c5]Hiroshi Suzuki, Zhongfeng Wang, Keshab K. Parhi:
A K=3, 2 Mbps low power turbo decoder for 3rd generation W-CDMA systems. CICC 2000: 39-42 - [c4]Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi:
High throughput low energy FEC/ARQ technique for short frame turbo codes. ICASSP 2000: 2653-2656 - [c3]Zhongfeng Wang, Keshab K. Parhi:
Decoding metrics and their applications in VLSI turbo decoders. ICASSP 2000: 3370-3373 - [c2]Zhongfeng Wang, Hiroshi Suzuki, Keshab K. Parhi:
Efficient approaches to improving performance of VLSI SOVA-based turbo decoders. ISCAS 2000: 287-290
1990 – 1999
- 1999
- [c1]S. Summerfield, Zhongfeng Wang, Keshab K. Parhi:
Area-power-time efficient pipeline-interleaved architectures for wave digital filters. ISCAS (3) 1999: 343-346
Coauthor Index
[j147] [j141] [c196] [c189] [c188] [i36] [i35] [i30] [j115] [j114] [c177] [i25] [j106] [j98] [c175] [c164] [c163] [c161] [c160] [c151] [c149] [i20] [i15] [j91] [j88] [j87] [j86] [j85] [j82] [c137] [c135] [c134] [c132] [j79] [j77] [j76] [j75] [j74] [j73] [j72] [j69] [j68] [c130] [c126] [c125] [c123] [c122] [c120] [c116] [c115] [c114] [c113] [c112] [c111] [c109] [c106] [i10] [i9] [i8] [j66] [j65] [j64] [j63] [j62] [j60] [j59] [j58] [j57] [j56] [j55] [j54] [j53] [c105] [c104] [c103] [c102] [c101] [c100] [c99] [c98] [c97] [c96] [c95] [c94] [c93] [c92] [c89] [c88] [c87] [c86] [c85] [c84] [i6] [i5] [i4] [i3] [j49] [j48] [j47] [j46] [j43] [j42] [j41] [c83] [c82] [c81] [c80] [c79] [c77] [c76] [c75] [c74] [c73] [c72] [c71] [c70] [i2] [j34] [j32] [c67] [c65] [c64] [c63] [c60] [c59] [c55] [c54] [c53] [j23] [j22] [j21] [j18] [j16] [j15] [c38] [c34] [c30]
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Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
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OpenAlex data
Load additional information about publications from 
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last updated on 2024-10-18 20:33 CEST by the dblp team
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