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ORCID12th ASICON 2017: Guiyang, China
- Yajie Qin, Zhiliang Hong, Ting-Ao Tang:
12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017. IEEE 2017, ISBN 978-1-5090-6625-4 - Franco Maloberti:
Keynote speech: Data converters for mobile and autonomous applications. XIV-XXI - Juin J. Liou:
Tutorial sessions: Electrostatic discharge protection of consumer electronics: Challenges and solutions. XXII-XXVI - Chun-Yen Chang, Chia-Chi Fan, Chien Liu, Yu-Chien Chiu, Chun-Hu Cheng:
High speed negative capacitance ferroelectric memory. 1-5 - TianShen Tang, Hao Ni, Zijian Zhao, Yao Zhou:
Development trends of embedded NVM technology. 6-11 - Amr M. S. Tosson, Shimeng Yu
, Mohab H. Anis, Lan Wei:
1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays. 12-15 - Yun Yin, Junlin Gou, Junyi Wang, Yarong Fu, Xiaoyong Xue, Yinyin Lin:
ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations. 16-19 - Yun Li, Haihua Shen, Ce Li, Feng Zhang:
An efficient parity rearrangement coding scheme for RRAM thermal crosstalk effects. 20-23 - Akira Matsuzawa, Masaya Miyahara:
SAR+ΔΣ ADC with open-loop integrator using dynamic amplifier. 24-27 - Zhiyuan Dai, Hang Hu, Manxin Li, Fan Ye, Junyan Ren:
A 0.87 mW 7MHz-BW 76dB-SNDR passive noise-shaping modulator based on a SAR ADC. 28-31 - Xiaoqing Chen, Fan Ye, Junyan Ren:
A 13-bit non-binary weighted SAR ADC with bridge structure using digital calibration for capacitor weight error. 32-35 - Bao Li, Long Zhao, Yuhua Cheng:
Auxiliary testability design schemes for CMOS DACs with ultrahigh sampling rates. 36-39 - Yumei Ma, Mengfei Ji, Yuping Guo, Yuchun Chang:
A 101 dB SNDR 3.7mW switched-capacitor ΣΔ ADC using tri-level quantization. 40-43 - Yan Ye, Weili Han, Haiyue Yan, Fujiang Lin:
A highly linear voltage-to-time converter with variable conversion gain for time-based ADCs. 44-47 - Yongsheng Wang, Yang Liu, Xunzhi Zhou, Anyi Wang, Bei Cao, Fengchang Lai:
An on-chip signal conditioning delta-sigma ADC for micro-mechanical gyroscope applications. 48-51 - Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi:
Soft error tolerant latch designs with low power consumption (invited paper). 52-55 - Runsheng Wang, Xiaobo Jiang, Shaofeng Guo, Ru Huang:
How close to the CMOS voltage scaling limit for FinFET technology? - Near-threshold computing and stochastic computing. 56-59 - Gang Li, Pengjun Wang, Yuejun Zhang:
A highly reliable lightweight PUF circuit with temperature and voltage compensated for secure chip identification. 60-63 - Daiki Asai, Masao Yanagisawa, Nozomu Togawa:
Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems. 64-67 - Ya-Bei Fang, Pei-Yuan Chou, Bo-Hao Chen, Tay-Jyi Lin, Jinn-Shyan Wang:
An all-n-type dynamic adder for ultra-low-leakage IoT devices. 68-71 - Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng:
A new error masking flip-flop with one cycle correction penalty. 72-75 - Wei He, Hengyang Zhao, Zhongdong Qi, Hai-Bao Chen, Sheldon X.-D. Tan:
Fast two-dimensional finite element analysis for power network DC integrity checks of PCBs. 76-79 - En-Jui Chang, An-Yeu Wu:
Overview of high-efficiency ant colony optimization (ACO)-based adaptive routings for traffic balancing in network-on-chip systems. 80-83 - Ye Huang, Xingquan Li, Wenxing Zhu, Jianli Chen:
Cut redistribution and DSA template assignment for unidirectional design. 84-87 - Ludan Yang, Weiwei Pan, Zheng Shi, Yongjun Zheng:
A novel layout automation flow to facilitate test chip design for standard cell characterization. 88-91 - Jiangtao Peng, Hai-Bao Chen, Hengyang Zhao, Zeyu Sun, Sheldon X.-D. Tan:
Dynamic temperature-aware reliability modeling for multi-branch interconnect trees. 92-95 - Zhigang Li, Jinglei Huang, Qi Xu, Song Chen:
Integer linear programming based fault-tolerant topology synthesis for application-specific NoC. 96-99 - Patricia Desgreys, Venkata Narasimha Manyam, Kelly Tchambake, Dang-Kièn Germain Pham, Chadi Jabbour:
Wideband power amplifier predistortion: Trends, challenges and solutions. 100-103 - Haijun Shao, Dan Fan, Pan Xue, Hongguang Zhang, Yilei Shen, Yumei Huang, Gan Guo, Zhiliang Hong:
A LTE digital mixer with 25% duty quadrature 4-phase clocks. 104-107 - Zhao Wang, Dihu Chen, Jianping Guo:
A CMOS transceiver RFIC for China geo-radio standard. 108-111 - Jingxuan Chen, Wai Tung Ng:
Design trends in smart gate driver ICs for power MOSFETs and IGBTs. 112-115 - Long Zhao, Feng Zou, Josh Yang, Tianshen Tang, Yuhua Cheng:
Analysis and characterization of process/layout impacts on the performance of high-speed analog circuits. 116-119 - Qinmiao Kang, Zhifeng Xie, Yongquan Liu, Ming Zhou:
A 0.18 μ m high-voltage area efficient integrated gate driver for piston engine fuel injection control SoC. 120-123 - Xin Liu, Yu Liu, Yanbin Xiao, Xiaohua Fan, Haiying Zhang:
An output-capacitor-less low-dropout regulator with transient-improved technique. 124-127 - Haobo Ruan, Tingyuan Yan, Yumei Huang:
A high-efficiency class e power amplifier with integrated finite DC feed inductance. 128-131 - Ruihan Pei, Jia Liu, Xian Tang, Fule Li, Zhihua Wang:
A low-offset dynamic comparator with input offset-cancellation. 132-135 - An Chen:
Cooptimization of emerging devices and architectures for energy-efficient computing. 136-139 - Chunmeng Dou, Wei-Hao Chen, Yi-Ju Chen, Huan-Ting Lin, Wei-Yu Lin, Mon-Shu Ho, Meng-Fan Chang:
Challenges of emerging memory and memristor based circuits: Nonvolatile logics, IoT security, deep learning and neuromorphic computing. 140-143 - Qingxi Duan, Teng Zhang, Minghui Yin, Caidie Cheng, Liying Xu, Yuchao Yang, Ru Huang:
Switching dynamics and computing applications of memristors: An overview. 144-147 - Qiang Chen, Chen Xin, Chenglong Zou, Xin'an Wang, Bo Wang:
A low bit-width parameter representation method for hardware-oriented convolution neural networks. 148-151 - Sujuan Liu, Ning Lyu, ZiSheng Wang:
High-speed FPGA implementation of orthogonal matching pursuit for analog to information converter. 152-155 - Domenico Rossi:
Looking back and forward: The execution dilemma and the importance of innovation in the semiconductor industry. 156-159 - Xiaoxu Kang, Limin Zhu, Xingwang Zhu, Qingyun Zuo, Xiaolan Zhong, Shoumian Chen, Yuhang Zhao, Shanshan Liu, Hanwei Lu, Jianmin Wang, Wei Wang, Bo Zhang:
Development and characterization of TaN thin film resistor with CMOS compatible fabrication process. 160-162 - Liang Zheng, Lin-Jie Yu, Lin Chen, Qing-Qing Sun, Wei Huang, Hao Zhu, David Wei Zhang:
Vertical power diodes based on bulk GaN substrates. 163-166 - Tailong Xu, Feng Xue, Zhikuang Cai, Xinning Liu, Shuo Meng:
A harmonic-free cell-based all-digital delay-locked loop for die-to-die clock synchronization of 3-D IC. 167-170 - Chengying Chen, Liming Chen, Xinghua Wang, Feng Zhang:
A 76μW, 58-dB SNDR analog front-end chip for implantable intraocular pressure detection. 171-174 - Wenhui Li, Awei Zhang, Weiwei Chen:
Design of a voltage-tunable pre-emphasis circuit utilizing a pseudo-differential cascode architecture. 175-178 - Hang Hu, Zhiyuan Dai, Manxin Li, Fan Ye, Junyan Ren:
A 320MS/s 7-b flash-SAR ADC with preamplifier sharing technique. 179-182 - Leiou Wang, Donghui Wang:
A gain factor controlled SUMPLE algorithm and system. 183-186 - Xu Yan, Lu Yang, Hao Zhang, Jili Zhang, Fujiang Lin:
A 1.0-7.0 GHz inductorless RF mixer with multiple feedback and active load in 40-nm CMOS. 187-190 - Longmei Nan, Xiaoyang Zeng, Zhouchuang Wang, Yiran Du, Wei Li:
Research of a reconfigurable coarse-grained cryptographic processing unit based on different operation similar structure. 191-194 - Zheng-Yuan Su, Jun Wu, Yao Yao, Min-Zhi Lin, Zhi-Yuan Ye, Peng-Fei Wang:
A novel vertical semi-floating gate transistor for high-density ultrafast memory. 195-198 - Jiangtao Gu, Bo Wang, Chao Zhang, Tingbing Ouyang, Lizhao Gao:
A novel programmable pulse-broadening time amplifier controlled by node capacitance. 199-202 - Tian-Yu Wang, Lin-Jie Yu, Lin Chen, Hao Liu, Hao Zhu, Qing-Qing Sun, Shi-Jin Ding, Peng Zhou, David Wei Zhang:
Atomic layer deposited Hf0.5Zr0.5O2-based flexible RRAM. 203-206 - Zizhao Liu, Tao Pan, Song Jia, Uan Wang:
Design of a novel ternary SRAM sense amplifier using CNFET. 207-210 - Xiaoqiang Lv, Yimao Cai, Yuchao Yang, Zhizhen Yu, Yichen Fang, Zongwei Wang, Lindong Wu, Jianfeng Liu, Wanrong Zhang, Ru Huang:
A neural network circuit with associative learning and forgetting process based on memristor neuromorphic device. 211-214 - Ping Luo, Kangle Wang, Shuangjie Qiu, Zelang Liu, Long Huang:
A 40V monolithic ultrasonic motor driver. 215-218 - Zhongshan Zheng, Zhentao Li, Gengsheng Chen, Jiajun Luo, Zhengsheng Han:
Roles of the gate length and width of the transistors in increasing the single event upset resistance of SRAM cells. 219-221 - Liyi Xiao, Chunhua Qi, Tianqi Wang, Hongchen Li, Jiaqiang Li:
Low-cost resilient radiation hardened flip-flop design. 222-225 - Huizi Zhang, Chang Wu, Xiao Hu:
Heterogeneous computing for CNN. 226-229 - Jun Qiao, Xiao Wang, Yaohong Zhao:
Optimization of operational amplifier settling time by adjusting secondary poles based on gm/ID design. 230-232 - Zhen Zhu, Emma Salmi, Sauli Virtanen:
Residual stress study of thin films deposited by atomic layer deposition. 233-236 - Zhiwei Li, Yan Li, Song Chen, Feng Wu:
A fully pipelined hardware architecture for convolutional neural network with low memory usage and DRAM bandwidth. 237-240 - Hengzhou Yuan, Jianjun Chen, Bin Liang, Yang Guo:
A radiation hardened low-noise voltage-controlled-oscillator using negative feedback based multipath- current-releasing technology. 241-244 - Yimin Wu, Yongzhen Chen, Manxin Li, Fan Ye, Junyan Ren:
A stacked-packaged 16-channel ADC for ultrasound application. 245-248 - Haisheng Qian, Guangxi Hu, Laigui Hu, Xing Zhou, Ran Liu, Li-Rong Zheng:
Analytical models for channel potential and drain current in AlGaN/GaN HEMT devices. 249-251 - Junhui Li, Liji Wu, Xiangmin Zhang:
An efficient HMAC processor based on the SHA-3 HASH function. 252-255 - Hansheng Wang, Minghui Zhang, Weiliang He, Lu Tang, Bin Jiang:
An improved equivalent circuit model for antenna: Modeling and parameter extraction. 256-258 - Xiang Ge, Hengliang Zhu, Fan Yang, Lingli Wang, Xuan Zeng:
Parallel sparse LU decomposition using FPGA with an efficient cache architecture. 259-262 - Xiaoqing Liu, Anping He, Caihong Li, Guangbo Feng, Jilin Zhang:
Study of 64-bit booth asynchronous multiplier based on FPGA. 263-266 - Liang Li, Ruizhi Sun, Ruoxi Wang, Fanjun Zang, Tao Jiang, Yang Li, Xinyang Wang, Yuchun Chang:
A 20MHz CTIA ROIC for InGaAs focal plane array. 267-270 - Mengting Li, Wenhao Sun, Zhimin Lu, Song Chen, Feng Wu:
Memristor-based material implication logic design for full adders. 271-274 - Xiudeng Wang, Xiaojing Zha, Yonggen Tu, Shi Ge, Yidie Ye, Yinshui Xia:
A synchronous charge extraction piezoelectric energy harvesting circuit based on precision active control peak detection with supplement energy. 275-278 - Min Liu, Ying Jian Yan, Wei Li:
Implementation and optimization of A5-1 algorithm on coarse-grained reconfigurable cryptographic logic array. 279-282 - Yewen Ni, Xiaoxin Cui, Tian Wang, Yuanning Fan, Qiankun Han, Kefei Liu, Xiaole Cui:
Improving DFA on AES using all-fault ciphertexts. 283-286 - Fan Feng, Li Li, Kun Wang, Feng Han, Hongbing Pan, Wei Li:
Application space exploration of a multi-fabric reconfigurable system. 287-290 - Jiaqi Yang, Jili Zhang, Xuefei Bai, Fujiang Lin:
A noise-shaping SAR ADC with dual error-feedback paths and alternate DACs. 291-294 - Yongzhen Chen, Yimin Wu, Fubiao Cao, Fan Ye, Junyan Ren:
A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs. 295-298 - Chunsheng Guo, Ju Meng, Zhiheng Liao, Shiwei Feng, Xun Wang, Lin Luo:
Influence of heat source size on thermal resistance of AlGaN/GaN HEMT. 299-302 - Fang-Fa Fu, Na Niu, Xiao-He Xian, Jinxiang Wang, Fengchang Lai:
An optimized topology reconfiguration bidirectional searching fault-tolerant algorithm for REmesh network-on-chip. 303-306 - Chenyang Kong, Xiaodong Liu, Weigang Xu, Zhangwen Tang:
A 1.0-to-2.4GHz wideband VCO with uniform sub-band interval and constant tuning gain. 307-310 - Jinghao Ye, Youhua Shi, Nozomu Togawa, Masao Yanagisawa:
A low cost and high speed CSD-based symmetric transpose block FIR implementation. 311-314 - Ying Zhang, Yujie Huang, Jun Han, Xiaoyang Zeng:
FPGA-based efficient implementation of SURF algorithm. 315-318 - Yujie Cai, Xin Li, Jun Han, Xiaoyang Zeng:
A configurable nonlinear operation unit for neural network accelerator. 319-322 - Chuanliang Kang, Pei Yang, Jian Wang, Jinmei Lai:
A deep research on the chip verification platform based on network. 323-326 - Jia-Wei Ma, Xuguang Guan, Tong Zhou, Tao Sun:
A new countermeasure against side channel attack for HMAC-SM3 hardware. 327-330 - Li Ding, Wenbo Yin:
A fully-pipelined hash table achieving low-latency and high throughput key-value retrieving system. 331-334 - Dongsheng Liu, Jiao Wang, Xiangcheng Sun, Jin Yan, Hi Lin:
A low input power charge pump for passive UHF RFID applications. 335-338 - Jia-wei Tan, Yang Guo, Jianjun Chen, Hengzhou Yuan, Xi Chen:
A state recovery design against single-event transient in high-speed phase interpolation clock and data recovery circuit. 339-342 - Lin-Jie Yu, Tian-Yu Wang, Lin Chen, Hao Zhu, Qing-Qing Sun, Shi-Jin Ding, Peng Zhou, David Wei Zhang:
Graphite planar resistive switching memory and its application in pattern recognition. 343-346 - Yanling Zhou, Yunyao Yan, Wei Yan:
A method to speed up VLSI hierarchical physical design in floorplanning. 347-350 - Xuejiao Ma, Yinshui Xia:
Power optimization based on dual-logic using And-Xor-Inverter Graph. 351-354 - Xin Ming, Xuan Zhang, Di Gao, Jia-Hao Zhang, Bo Zhang:
PSR-enhanced low-dropout regulator using feedforward supply noise rejection technique. 355-358 - Rongsheng Zhang, Liyi Xiao, Jie Li:
A fast and accurate fault injection platform for SRAM-based FPGAs. 359-362 - Liyi Xiao, Anlong Li, Xuebing Cao, Hongchen Li, Rongsheng Zhang, Jie Li, Tianqi Wang:
A method to estimate cross-section of circuits at RTL levels. 363-366 - Yongsheng Wang, Xinzhi Li, Zhixin Zhang, Fengchang Lai:
A low gain error two-stage dB-linear variable gain amplifier in 0.35μm CMOS process. 367-370 - Hui Shen, Huiwen Yuan, Sitong Bu, Mingyue He, Daming Huang:
Low frequency noise characteristics in p-Type MOSFET with multilayer WSe2 channel and Al2O3 back gate dielectric. 371-374 - Yaopeng Kang, Pengjun Wang, Yuejun Zhang, Gang Li:
Design of ternary pulsed reversible counter based on CNFET. 375-378 - Mingbo Wang, Pengjun Wang, Qiang Fu, Huihong Zhang:
Delay and area optimization for FPRM circuits based on MSPSO algorithm. 379-382 - Baofa Huang, Ningyuan Yin, Zhiyi Yu:
The write deduplication mechanism based on a novel low-power data latched sense amplifier for a magnetic tunnel junction based non-volatile memory. 383-386 - Dongsheng Liu, Xiangcheng Sun, Jiao Wang, Fan Kang:
Implementation of an energy-efficient digital baseband controller compatible with EPC Class-1 Gen-2 standard. 387-390 - Yongsheng Wang, Shanshan Li, Ruoyang Wang, Xiaowei Liu:
LMS-FIR based digital background calibration for the four-channel time-interleaved ADC. 391-394 - Qichao He, Xiong Zhou, Qiang Li:
Optimization of the amplifier's input-referred noise for high resolution comparators. 395-397 - Yue Shi, Hongming Yu, Zekun Zhou:
A self-powered supply circuit for switching mode power supply. 398-401 - Jiaqi Gu, Ruoyao Wang, Jian Wang, Jinmei Lai, Qinghua Duan:
Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration. 402-405 - Xiaodong Liu, Chenyang Kong, Yifan Gao, Zhangwen Tang:
A 0.07-ppm/step differential digitally controlled crystal oscillator with guaranteed monotonicity. 406-409 - Yong Gu, Xuguang Guan, Tong Zhou:
The configurable current flattening circuit for DPA countermeasures. 410-413 - Wei Huang, Zhonghe Guo, Xiaohua Song, Fei Sun:
A cluster-scalable VLIW cryptography processor with high performance and energy efficiency. 414-417 - Toshiro Hiramoto, Tomoko Mizutani, Kiyoshi Takeuchi, Masaharu Kobayashi:
Parallel nonvolatile programming of power-up states of SRAM cells. 418-421 - You Yin:
Phase-change materials and memory devices for IoT application. 422-425 - Fujun Bai, Baoyu Xiong, Xiaofei Xue, Weizhe Song, Baofeng Wu, Ni Fu, Bing Yu, Huifu Duan, Xiaowei Han, Alessandro Minzoni, Qiwei Ren:
A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power. 426-428 - Jinghui Han, Yao Zhou, Hao Ni, Xiao Zheng, Yi Zhao:
A 55nm logic process compatible p-flash memory array fully demonstrated with high reliability. 429-432 - Kai-Ping Chang, Han-Hsiang Tai, Jer-Chyi Wang, Chao-Sung Lai:
Graphene nanodots with high-k dielectrics for flash memory applications. 433-435 - Jan Van der Spiegel, Milin Zhang, Xilin Liu:
The next-generation brain machine interface system for neuroscience research and neuroprosthetics development. 436-439 - Yingdan Li, Fei Chen, Zhuoyi Sun, Zhaoyang Weng, Xian Tang, Hanjun Jiang, Zhihua Wang:
System architecture of a smart binaural hearing aid using a mobile computing platform. 440-443 - Chenjie Dong, Han Jin, IkHwan Kim, Chenyu Wang, Yajie Qin, Li-Rong Zheng:
An area efficient low power ECoG front-end chip for digitalized subdural grid.