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Semantic ScholarISCAS 2001: Sydney, Australia - Volume 4
Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001. IEEE 2001, ISBN 0-7803-6685-9- Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang:
Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. 1-4 - A. B. M. Harun-ur Rashid, M. Karim, Syed Mahfuzul Aziz:
Testing complementary pass-transistor logic circuits. 5-8 - Abdelhakim Khouas, Anne Derieux:
FDP: fault detection probability function for analog circuits. 17-20 - Zahir M. Hussain, Boualem Boashash:
Statistical analysis of the time-delay digital tanlock loop in the presence of Gaussian noise. 21-24 - Tung-Sang Ng, Kun-Wah Yip, Chin-Long Cheng:
An all-lag rotating-reference correlator and its efficient implementation. 25-28 - Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang:
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. 33-36 - Andrew C. McCormick, Peter M. Grant, John S. Thompson, Tughrul Arslan, Ahmet T. Erdogan:
A low power MMSE receiver architecture for multi-carrier CDMA. 41-44 - D. Leon, Sina Balkir, Michael W. Hoffman, Lance C. Pérez:
Robust chaotic PN sequence generation techniques. 53-56 - Yeong-Kang Lai, Yu-Chuan Shu:
VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation. 57-60 - David Garrett, Mircea R. Stan:
A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications. 61-64 - Zhipei Chi, Leilei Song, Keshab K. Parhi:
A study on the performance, complexity tradeoffs of block turbo decoder design. 65-68 - Håkan Bengtson, Christer Svensson:
3V CMOS 0.35 µ transimpedance receiver for optical applications. 69-71 - Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, Chu King, Chien-Hsiung Lee, Tim Liu:
A serial link transceiver for USB2 high-speed mode. 72-75 - Chua-Chin Wang, Po-Ming Lee, Rong-Chin Lee, Chenn-Jung Huang:
A 1.25 GHz 32-bit tree-structured carry lookahead adder. 80-83 - Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour:
A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder. 84-87 - Andreas Wassatsch, Dirk Timmermann:
Scalable counter architecture for a pre-loadable 1 GHz@0.6 um/5V pre-scaler in TSPC. 92-95 - Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez, Saeid Nooshabadi:
A compact layout technique to minimize high frequency switching effects in high speed circuits. 96-99 - H. Zarei, Omid Shoaei, Seid Mehdi Fakhraie:
A low-power fully integrated Gaussian-MSK modulator based on the sigma-delta fractional-N frequency synthesis. 100-103 - Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo:
CML ring oscillators: oscillation frequency. 112-115 - F. Xavier Moncunill-Geniz, Orestes Mas-Casals, Pere Palà-Schönwälder:
A comparative analysis of direct-sequence spread-spectrum super-regenerative architectures. 120-123 - Kari Stadius, P. Jarvio, Petteri Paatsila, Kari Halonen:
Image-reject receivers with image-selection functionality. 124-127 - Sridhar Rajagopal, Joseph R. Cavallaro:
A bit-streaming, pipelined multiuser detector for wireless communication receivers. 128-131 - F. S. Tsai, Chen-Yi Lee:
A novel single-bit input all digital synchronizer and demodulator baseband processor for fast frequency hopping system. 132-135 - Satoshi Makido, Takaya Yamazato, Hiraku Okada, Masaaki Katayama, Akira Ogawa:
A design of source matched MAP receiver for image transmission. 136-139 - Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni:
A CMOS differential logic for low-power and high-speed applications. 140-143 - Frank Grassert, Dirk Timmermann:
Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs. 144-147 - Hongchin Lin, Yi-Fan Chen, Hsien-Chih She:
A low-power 3-phase half rail pass-gate differential logic. 148-151 - Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang:
Skew-tolerant high-speed (STHS) domino logic. 154-157 - Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Noise constrained power optimization for dual VT domino logic. 158-161 - I. Thoidis, Dimitrios Soudris, J. M. Fernandez, Adonios Thanailakis:
The circuit design of multiple-valued logic voltage-mode adders. 162-165 - Henrik Eriksson, Per Larsson-Edefors, William P. Marnane:
A regular parallel multiplier which utilizes multiple carry-propagate adders. 166-169 - Pasi Liljeberg, Juha Plosila, Jouni Isoaho:
Asynchronous interface for locally clocked modules in ULSI systems. 170-173 - Nazmy Abaskharoun, Mohamed Hafed, Gordon W. Roberts:
Strategies for on-chip sub-nanosecond signal capture and timing measurements. 174-177 - Artur Wróblewski, Otto Schumacher, Christian V. Schimpfle, Josef A. Nossek:
Minimizing gate capacitances with transistor sizing. 186-189 - Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang:
A low-cost CMOS time interval measurement core. 190-193 - T. Santti, Jouni Isoaho:
Modified SRCMOS cell for high-throughput wave-pipelined arithmetic units. 194-197 - Felix Lustenberger, Hans-Andrea Loeliger:
On mismatch errors in analog-VLSI error correcting decoders. 198-201 - Tong Zhang, Zhongfeng Wang, Keshab K. Parhi:
On finite precision implementation of low density parity check codes decoder. 202-205 - Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu:
VLSI architecture of extended in-place path metric update for Viterbi decoders. 206-209 - Ayman A. Fayed, Magdy A. Bayoumi:
A low power 10-transistor full adder cell for embedded architectures. 226-229 - Kasin Vichienchom, Mark Clements, Wentai Liu:
A multi-gigabit CMOS data recovery circuit using an analog parallel sampling technique. 238-241 - R. K. Jain, R. Frenzel, M. Terschluse, P. K. Pandey, S. H. Low, B. Sukumaran, L. M. Lam:
System-on-chip design of a four-port ADSL-lite Data DSP. 242-245 - Yuyu Chang, Jack Wills, John Choma Jr.:
On-chip automatic direct tuning circuitry based on the synchronous rectification scheme for CMOS gigahertz band front-end filters. 246-249 - Scott D. Huss, John Bennett:
An efficient model for twisted-pair cables with discontinuities and stubs for discrete time simulations. 254-257 - John C. McEachen, Ow Kong Chung, Lim Chin Thong:
A system level description and model of Signaling System No 7. 258-261 - Jin-Ku Kang, Dong-Hee Kim:
A CMOS clock and data recovery with two-XOR phase-frequency detector circuit. 266-269 - B. Siddik Yarman, Ahmet Aksen:
A reflectance-based computer aided modelling tool for high speed/high frequency communication systems. 270-273 - Ronald P. Luijten, Antonius P. J. Engbersen, Cyriel Minkenberg:
Shared memory switching + virtual output queuing: A robust and scalable switch. 274-277 - Mostafa I. Abd-El-Barr, C. Sundarram, A. S. Almulhem:
VLSI considerations in the design of k-ary n-cube interconnection networks. 278-281 - Di He, Chen He, Ling-ge Jiang, Hong-Wen Zhu, Guang-Rui Hu:
Phase tracking of CDMA spreading sequences using dynamic chaotic synchronization. 282-285 - Chin-Liang Wang, Ming-Hung Li, Kuo-Ming Wu, Kwei-Liang Hwang:
Adaptive interference suppression with power control for CDMA systems. 286-289 - Kyungtae Han, Iksu Eo, Kyungsu Kim, Hanjin Cho:
Numerical word-length optimization for CDMA demodulator. 290-293 - X. M. Wang, Wu-Sheng Lu, Andreas Antoniou:
A near-optimal multiuser detector for CDMA channels using semidefinite programming relaxation. 298-301 - Tuomas Järvinen, Jarmo Takala, David Akopian, Jukka Saarinen:
Register-based multi-port perfect shuffle networks. 306-309 - Hiroshi Nakada, Hideyuki Ito, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri, Tsunemichi Shiozawa, Norbert Imlig:
Self-reorganising systems on VLSI circuits. 310-313 - Yew-San Lee, Cheng-Mou Yu, Chen-Yi Lee:
Error resilient hybrid variable length codec with tough error synchronization for wireless image transmission. 326-329 - Wei-Hsin Chang, Yew-San Lee, Wen-Shiaw Peng, Chen-Yi Lee:
A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme. 330-333 - Christos Drosos, Chrissavgi Dre, Spyros Blionas, Dimitrios Soudris:
On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal. 334-337 - Li-Hsun Chen, Oscal T.-C. Chen:
A low-complexity and high-speed Booth-algorithm FIR architecture. 338-341 - Adel-Omar Dahmane, Daniel Massicotte, Leszek Szczecinski:
A VLSI architecture of a piecewise RBF decision feedback channel equalizer. 342-345 - Marco Re, Alberto Nannarelli, Gian-Carlo Cardarilli, Roberto Lojacono:
FPGA realization of RNS to binary signed conversion architecture. 350-353 - Yin-Tsung Hwang, Jih-Cheng Han, Jing-Yi Liu:
Design and implementation of channel equalizers for block transmission systems. 354-357 - Ching-Chi Chang, Chien-Chih Lin, Muh-Tian Shiue, Chorng-Kuang Wang:
A wide pull-in range fast acquisition hardware-sharing two-fold carrier recovery loop. 358-361 - Waleed M. Younis, Naofal Al-Dhahir:
FIR prefilter design for MLSE equalization of space-time-coded transmission over multipath fading channels. 362-365 - Roberto López-Valcarce, Soura Dasgupta:
Second order statistics based blind channel equalization with correlated sources. 366-369 - Ediz Çetin, Izzet Kale, Richard C. S. Morling:
Adaptive compensation of analog front-end I/Q mismatches in digital receivers. 370-373 - Xiaopeng Li, Mohammed Ismail:
A single-chip CMOS front-end receiver architecture for multi-standard wireless applications. 374-377 - Tang Jing Jung, King Sau Cheung, J. Lau:
A 2.4 GHz four port mixer for direct conversion used in telemetering. 378-381 - Kalle Kivekäs, Aarno Pärssinen, Jarkko Jussila, Jussi Ryynänen, Kari Halonen:
Design of low-voltage active mixer for direct conversion receivers. 382-385 - Zhaofeng Zhang, L. Tsui, Zhiheng Chen, J. Lau:
A CMOS self-mixing-free front-end for direct conversion applications. 386-389 - Hung Yan Cheung, King Sau Cheung, J. Lau:
A low power monolithic AGC with automatic DC offset cancellation for direct conversion hybrid CDMA transceiver used in telemetering. 390-393 - Harri Lampinen, Olli Vainio:
Dynamically biased current sensor for current-sensing completion detection. 394-397 - Yavuz Kiliç, Mark Zwolinski:
Process variation independent built-in current sensor for analogue built-in self-test. 398-401 - Gaetano Palumbo, Domenico Pappalardo, M. Gaibotti:
Modeling and minimization of power consumption in charge pump circuits. 402-405 - Joshua L. Garrett, Mircea R. Stan:
Active threshold compensation circuit for improved performance in cooled CMOS systems. 410-413 - Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Power trends and performance characterization of 3-dimensional integration. 414-417 - Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou:
A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. 422-425 - Luca Fanucci, Roberto Roncella, Roberto Saletti:
Non-linearity reduction technique for delay-locked delay-lines. 430-433 - Martin Makundi, Vesa Välimäki, Timo I. Laakso:
Closed-form design of tunable fractional-delay allpass filter structures. 434-437 - Ming-Hwa Sheu, Ho-En Liao, Shih Tsung Kan, Ming-Der Shieh:
A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter. 446-449 - Thomas Magesacher, Per Ödling, Tomas Nordström, T. Lunberg, Mikael Isaksson, Per Ola Börjesson:
An adaptive mixed-signal narrowband interference canceller for wireline transmission systems. 450-453 - A. N. L. Chan, K. W. H. Ng, J. M. C. Wong, H. C. Luong:
A 1-V 2.4-GHz CMOS RF receiver front-end for Bluetooth application. 454-457 - Risto Kaunisto, P. Korpi, J. Kiraly, Kari Halonen:
A linear-control wide-band CMOS attenuator. 458-461 - Luca Fanucci, Giorgio D'Angelo, Andrea Monterastelli, Mario Paparo, Bruno Neri:
Fully integrated low-noise-amplifier with high quality factor L-C filter for 1.8 GHz wireless applications. 462-465 - J. C. Huang, Ro-Min Weng, Cheng-Chih Chang, Kang Hsu, Kun-Yi Lin:
A 2 V 2.4 GHz fully integrated CMOS LNA. 466-469 - Adiseno, Mohammed Ismail, H. K. Olsson:
Dual-loop cross-coupled feedback amplifier for low-IF integrated receiver architecture. 470-473 - Mohamed A. Elgamel, Ahmed M. Shams, Xi Xueling, Magdy A. Bayoumi:
Enhanced low power motion estimation VLSI architectures for video compression. 474-477 - Erno Salminen, Timo D. Hämäläinen, Tero Kangas, Kimmo Kuusilinna, Jukka Saarinen:
Interfacing multiple processors in a system-on-chip video encoder. 478-481 - Konstantina Karagianni, Thanos Stouraitis:
A vector processor for 3-D geometrical transformations. 482-485 - Stefan Getzlaff, Jörg Schreiter, Achim Graupner, René Schüffny:
A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing. 486-489 - William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria:
Fast system-level exploration of memory architectures driven by energy-delay metrics. 502-505 - Kah-Howe Tan, Wen Fung-Leong, S. Kadam, Michael A. Soderstrand, Louis G. Johnson:
Public-domain Matlab program to generate highly optimized VHDL for FPGA implementation. 514-517 - Li-Minn Ang, Hon Nin Cheung:
Hardware implementation of the depth first search bit stream SPIHT system. 518-521