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ORCIDISVLSI 2021: Tampa, FL, USA
- IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021, Tampa, FL, USA, July 7-9, 2021. IEEE 2021, ISBN 978-1-6654-3946-6
- Shatadal Chatterjee, Maryaradhiya Daimari, Sounak Roy:
A Fully Digital Foreground Calibration Technique of A Flash ADC. 1-6 - Fabian Kempf, Thomas Hartmann, Steffen Baehr, Jürgen Becker:
An Adaptive Lockstep Architecture for Mixed-Criticality Systems. 7-12 - Ke Huang, Md Toufiq Hasan Anik, Xinqiao Zhang, Naghmeh Karimi:
Real-Time IC Aging Prediction via On-Chip Sensors. 13-18 - Shiv Chandra Kumar, Siddharth R. K.
, Nithin Kumar Y. B., M. H. Vasantha:
A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications. 19-24 - Tiago Augusto Fontana, Erfan Aghaeekiasaraee, Renan Netto, Sheiny Fabre Almeida, Upma Gandhi, Aysa Fakheri Tabrizi, David T. Westwick, Laleh Behjat, José Luís Güntzel:
ILP-Based Global Routing Optimization with Cell Movements. 25-30 - Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
A Comparative Study of Specification Mining Methods for SoC Communication Traces. 31-36 - Mohammed Abderehman, Rupak Gupta, Chandan Karfa:
Reverse Engineering Register to Variable Mapping in High-level Synthesis. 37-42 - Masoud Shahshahani, Dinesh Bhatia:
Resource and Performance Estimation for CNN Models using Machine Learning. 43-48 - Chris Collinsworth, Sayed Ahmad Salehi:
Stochastic Number Generators with Minimum Probability Conversion Circuits. 49-54 - Keyue Deng, Hangxuan Cui, Jun Lin, Zhongfeng Wang:
Counter Random Gradient Descent Bit-Flipping Decoder for LDPC Codes. 55-60 - Martha Schnieber, Saman Fröhlich, Rolf Drechsler:
Depth Optimized Synthesis of Symmetric Boolean Functions. 61-66 - Adam Z. Foshie, Nishith N. Chakraborty, John J. Murray, Tanner J. Fowler, Mst Shamim Ara Shawkat, Garrett S. Rose:
A Multi-Context Neural Core Design for Reconfigurable Neuromorphic Arrays. 67-72 - Mateus Saquetti, Raphael Martins Brum, Bruno Zatt, Samuel Pagliarini, Weverton Cordeiro, José Rodrigo Azambuja:
A Terabit Hybrid FPGA-ASIC Platform for Switch Virtualization. 73-78 - Naveen Kumar Macha, Prerana Samant, Mostafizur Rahman:
Crosstalk Logic Circuits with Built-in Memory. 79-83 - Rahul Thapa, Bikal Lamichhane, Dongning Ma, Xun Jiao:
SpamHD: Memory-Efficient Text Spam Detection using Brain-Inspired Hyperdimensional Computing. 84-89 - Rahul Thapa, Dongning Ma, Xun Jiao:
HDXplore: Automated Blackbox Testing of Brain-Inspired Hyperdimensional Computing. 90-95 - Ryosuke Matsuo, Shin-ichi Minato:
BDD Variable Ordering for Minimizing Power Consumption of Optical Logic Circuits. 96-101 - John J. Murray, Adam Z. Foshie, Mst Shamim Ara Shawkat, Garrett S. Rose:
Scaling Constraints for Memristor-based Programmable Interconnect in Reconfigurable Computing Arrays. 102-107 - Mahdi Zahedi, Remon van Duijnen, Stephan Wong, Said Hamdioui:
Tile Architecture and Hardware Implementation for Computation-in-Memory. 108-113 - Quang-Linh Nguyen, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre:
On Preventing SAT Attack with Decoy Key-Inputs. 114-119 - Shakil Mahmud, Brooks Olney, Robert Karam:
An Extensible Evaluation Platform for FPGA Bitstream Obfuscation Security. 120-125 - Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu:
Lorax: Machine Learning-Based Oracle Reconstruction With Minimal I/O Patterns. 126-131 - Zhiming Zhang, Ivan Miketic, Emre Salman, Qiaoyan Yu:
Towards Enhancing Power-Analysis Attack Resilience for Logic Locking Techniques. 132-137 - Kyle Buettner, Alan D. George:
Heartbeat Classification with Spiking Neural Networks on the Loihi Neuromorphic Processor. 138-143 - Tongtong Yin, Wendong Mao, Jinming Lu, Zhongfeng Wang:
A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA. 144-149 - Jianghan Zhu, Bingzhen Chen, Zhitao Yang, Lingxiao Meng, Terry Tao Ye:
Analog Circuit Implementation of Neural Networks for In-Sensor Computing. 150-156 - John Reuben, Dietmar Fey:
Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles. 157-163 - Flavio Ponzina, Marco Rios, Giovanni Ansaloni, Alexandre Levisse, David Atienza:
A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs. 164-169 - Noureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory:
FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method. 170-175 - Sachin Bhat, Mingyu Li, Sounak Shaun Ghosh, Sourabh Kulkarni, Csaba Andras Moritz:
SkyBridge-3D-CMOS 2.0: IC Technology for Stacked-Transistor 3D ICs beyond FinFETs. 176-181 - Luyi Li, Jun Lin, Zhongfeng Wang:
PipeBSW: A Two-Stage Pipeline Structure for Banded Smith-Waterman Algorithm on FPGA. 182-187 - Mohammed E. Elbtity, Abhishek Singh, Brendan Reidy, Xiaochen Guo, Ramtin Zand:
An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devices. 188-193 - Yassmeen Elderhalli, Nahla A. El-Araby, Osman Hasan, Axel Jantsch, Sofiène Tahar:
Dynamic Fault Tree Models for FPGA Fault Tolerance and Reliability. 194-199 - Supreeth Mysore Shivanandamurthy, Ishan G. Thakkar, Sayed Ahmad Salehi:
ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing. 200-205 - Mahboobe Sadeghipour Roodsari, Hanieh Totonchi Asl, Zainalabedin Navabi:
n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM Accelerator. 206-211 - Qilin Si, M. Imtiaz Rashid, Benjamin Carrión Schäfer:
Micro-architecture Tuning for Dynamic Frequency Scaling in Coarse-Grain Runtime Reconfigurable Arrays with Adaptive Clock Domain Support. 212-217 - Yuk Wong, Zhenjiang Dong, Wei Zhang:
Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic. 218-223 - Tim Todman, Wayne Luk:
Custom enhancements to networked processor templates. 224-229 - Liancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang:
Analyzing the Design Space of Spatial Tensor Accelerators on FPGAs. 230-235 - William Unger, Liljana Babinkostova, Mike Borowczak, Robert Erbes:
Side-channel Leakage Assessment Metrics: A Case Study of GIFT Block Ciphers. 236-241 - Shaya Wolf, Hui Hu, Rafer Cooley, Mike Borowczak:
Stealing Machine Learning Parameters via Side Channel Power Attacks. 242-247 - Subashree Raja, Padmaja Bhamidipati, Xiaobang Liu, Ranga Vemuri:
Security Capsules: An Architecture for Post-Silicon Security Assertion Validation for Systems-on-Chip. 248-253 - Haikuo Shao, Jinming Lu, Jun Lin, Zhongfeng Wang:
An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training. 254-259 - Zhixin Pan, Prabhat Mishra:
Accelerating Spectral Normalization for Enhancing Robustness of Deep Neural Networks. 260-265 - Harideep Nair, John Paul Shen, James E. Smith:
A Microarchitecture Implementation Framework for Online Learning with Temporal Neural Networks. 266-271 - Jonas Krautter, Mehdi B. Tahoori:
Neural Networks as a Side-Channel Countermeasure: Challenges and Opportunities. 272-277 - Sandeep Sunkavilli, Zhiming Zhang, Qiaoyan Yu:
New Security Threats on FPGAs: From FPGA Design Tools Perspective. 278-283 - Shijin Duan, Wenhao Wang, Yukui Luo, Xiaolin Xu:
A Survey of Recent Attacks and Mitigation on FPGA Systems. 284-289 - Joel Mandebi Mbongue, Sujan Kumar Saha, Christophe Bobda:
A Security Architecture for Domain Isolation in Multi-Tenant Cloud FPGAs. 290-295 - Deepraj Soni, Ramesh Karri:
Efficient Hardware Implementation of PQC Primitives and PQC algorithms Using High-Level Synthesis. 296-301 - Adrian Tatulian, Ronald F. DeMara:
A Reconfigurable and Compact Spin-Based Analog Block for Generalizable nth Power and Root Computation. 302-307 - Jinhe Du, Ke Chen, Peipei Yin, Chenggang Yan, Weiqiang Liu:
Design of An Approximate FFT Processor Based on Approximate Complex Multipliers. 308-313 - Zachary Kahleifeh, Himanshu Thapliyal:
Low-Energy and CPA-Resistant Adiabatic CMOS/MTJ Logic for IoT Devices. 314-319 - Kuiqing He, Zhi Yang, Zhitai Yu, Jianglong Zhi, Zhaohao Wang, Yijiao Wang:
Proposal of A Novel Hybrid NAND-Like MRAM/DRAM Memory Architecture. 320-325 - Corentin Delacour, Stefania Carapezzi, Madeleine Abernot, Gabriele Boschetto, Nadine Azémard, Jérémie Salles, Thierry Gil, Aida Todri-Sanial:
Oscillatory Neural Networks for Edge AI Computing. 326-331 - Krithika Dhananjay, Emre Salman:
EQUAL: Efficient QUasi Adiabatic Logic for Enhanced Side-Channel Resistance. 332-337 - Ragh Kuttappa, Leo Filippini, Nicholas Sica, Baris Taskin:
Scalable Resonant Power Clock Generation for Adiabatic Logic Design. 338-342 - Muhammad Monir Hossain, Sajeed Mohammad, Jason Vosatka, Jeffery S. Allen, Monica Allen, Farimah Farahmandi, Fahim Rahman, Mark M. Tehranipoor:
HEXON: Protecting Firmware Using Hardware-Assisted Execution-Level Obfuscation. 343-349 - Matthew Lewandowski, Srinivas Katkoori:
Enhancing PRESENT-80 and Substitution-Permutation Network Cipher Security with Dynamic "Keyed" Permutation Networks. 350-355 - Mohammad Ebrahimabadi, Wassila Lalouani, Mohamed F. Younis, Naghmeh Karimi:
Countering PUF Modeling Attacks through Adversarial Machine Learning. 356-361 - Mottaqiallah Taouil, Cezar Reinbrecht, Said Hamdioui, Johanna Sepúlveda:
LightRoAD: Lightweight Rowhammer Attack Detector. 362-367 - Seungseok Nam, Emil Matús, Gerhard P. Fettweis:
Minimized Region of Path-search Algorithm for ASIP-based Connection Allocator in NoCs. 368-373 - Marina Yushkova, Alberto Sánchez, Angel de Castro:
Improved Polygon Method for HIL Simulations in Real Time. 374-377 - Sukanta Dey, Sukumar Nandi, Gaurav Trivedi:
Machine Learning for VLSI CAD: A Case Study in On-Chip Power Grid Design. 378-383 - Muhammad Awais, Marco Platzner:
MCTS-based Synthesis Towards Efficient Approximate Accelerators. 384-389 - Rajdeep Kumar Nath, Himanshu Thapliyal:
Wearable Health Monitoring System for Older Adults in a Smart Home Environment. 390-395 - Bradley Comar:
Implementation of a QPSK Symbol Synchronizer in Xilinx System Generator. 396-401 - Mohammadreza Esmali Nojehdeh, Sajjad Parvin, Mustafa Altun:
Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks. 402-405 - Sajjad Parvin, Mustafa Altun:
A Study on Hardware-Aware Training Techniques for Feedforward Artificial Neural Networks. 406-411 - Konstantinos G. Liakos, Georgios K. Georgakilas, Fotis C. Plessas:
Hardware Trojan Classification at Gate-level Netlists based on Area and Power Machine Learning Analysis. 412-417 - Vikas Pathak, Satyasai Jagannath Nanda, Amit Mahesh Joshi, Sitanshu Sekhar Sahu:
FPGA Implementation of High Speed Anti-notch Lattice filter for Exon Region Identification in Eukaryotic Genes. 418-421 - Peter Demetriou, Conrad J. Haupt, Ken J. Nixon:
A Quantum Variational Approach to Debugging Combinational Logic Circuits. 422-427 - Siyuan Niu, Aida Todri-Sanial:
Analyzing crosstalk error in the NISQ era. 428-430 - Nikita Acharya, Samah Mohamed Saeed:
Automated Flag Qubit Insertion for Reliable Quantum Circuit Output. 431-436 - Oumarou Oumarou, Alexandru Paler, Robert Basmadjian:
Fast quantum circuit simulation using hardware accelerated general purpose libraries. 437-440 - Andrew Haverly, Sonia López:
Implementation of Grover's Algorithm to Solve the Maximum Clique Problem. 441-446 - Danylo Lykov, Yuri Alexeev:
Importance of Diagonal Gates in Tensor Network Simulations. 447-452 - Rajdeep Kumar Nath, Himanshu Thapliyal, Travis S. Humble:
Quantum Annealing for Automated Feature Selection in Stress Detection. 453-457 - Samudra Dasgupta, Travis S. Humble:
Reproducibility in Quantum Computing. 458-461 - Meriam Gay Bautista, Zhi Jackie Yao, Anastasiia Butko, Mariam Kiran, Mekena Metcalf:
Towards Automated Superconducting Circuit Calibration using Deep Reinforcement Learning. 462-467
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