"A Memory Efficient Partially Parallel Decoder Architecture for ..."

Zhongfeng Wang, Zhiqiang Cui (2007)

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DOI: 10.1109/TED.2007.895247

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type: Journal Article

metadata version: 2023-04-24

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Zhongfeng Wang, Zhiqiang Cui:
A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 483-488 (2007)

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