"Efficient Hardware Architectures for Deep Convolutional Neural Network."

Jichen Wang, Jun Lin, Zhongfeng Wang (2018)

> Home

Details and statistics

DOI: 10.1109/TCSI.2017.2767204

access: closed

type: Journal Article

metadata version: 2023-04-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcas/WangLW18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/WangLW18
Jichen Wang, Jun Lin, Zhongfeng Wang:
Efficient Hardware Architectures for Deep Convolutional Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1941-1953 (2018)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.