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Books and Theses
- 2016
[b1]Shimeng Yu:
Resistive Random Access Memory (RRAM). Synthesis Lectures on Emerging Engineering Technologies, Morgan & Claypool Publishers 2016, ISBN 978-3-031-00902-0, pp. 1-79
Journal Articles
- 2024
- [j68]Shimeng Yu
, Tae-Hyeon Kim:
Semiconductor Memory Technologies: State-of-the-Art and Future Trends. Computer 57(4): 150-154 (2024) - [j67]Po-Kai Hsu, Vaidehi Garg, Anni Lu, Shimeng Yu:
A Heterogeneous Platform for 3D NAND-Based In-Memory Hyperdimensional Computing Engine for Genome Sequencing Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 71(4): 1628-1637 (2024) - [j66]Junmo Lee, Anni Lu, Wantong Li, Shimeng Yu:
NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node. IEEE Trans. Circuits Syst. I Regul. Pap. 71(4): 1733-1744 (2024) - [j65]Xiaoxuan Yang, Zhangyang Wang, X. Sharon Hu, Chris H. Kim, Shimeng Yu, Miroslav Pajic, Rajit Manohar, Yiran Chen, Hai Helen Li:
Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1683-1689 (2024) - [j64]Yandong Luo, Johan Vanderhaegen, Oleg Rybakov, Martin Kraemer, Niel Warren, Shimeng Yu:
A FeFET-Based ADC Offset Robust Compute-In-Memory Architecture for Streaming Keyword Spotting (KWS). IEEE Trans. Emerg. Top. Comput. 12(1): 23-34 (2024) - [j63]Yandong Luo, Shimeng Yu:
H3D-Transformer: A Heterogeneous 3D (H3D) Computing Platform for Transformer Model Acceleration on Edge Devices. ACM Trans. Design Autom. Electr. Syst. 29(3): 47:1-47:19 (2024) - [j62]Yuan-Chun Luo, Anni Lu, Yandong Luo, Sou-Chi Chang, Uygar Avci, Shimeng Yu:
Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1696-1703 (2024) - [j61]Yuan-Chun Luo, Anni Lu, Janak Sharda, Moritz Scherer, Jorge Tomás Gómez, Syed Shakib Sarwar, Ziyun Li, Reid Frederick Pinkham, Barbara De Salvo, Shimeng Yu:
Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1718-1725 (2024) - 2023
- [j60]Anni Lu, Jae Hur, Yuan-Chun Luo, Hai Li, Dmitri E. Nikonov, Ian A. Young, Yang-Kyu Choi, Shimeng Yu:
Scalable In-Memory Clustered Annealer With Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 422-435 (2023) - [j59]Hongwu Jiang, Shanshi Huang, Wantong Li, Shimeng Yu:
ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 353-363 (2023) - [j58]Janak Sharda, Wantong Li, Qiucheng Wu, Shiyu Chang, Shimeng Yu:
Temporal Frame Filtering for Autonomous Driving Using 3D-Stacked Global Shutter CIS With IWO Buffer Memory and Near-Pixel Compute. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 2074-2084 (2023) - [j57]Shanshi Huang, Hongwu Jiang, Shimeng Yu:
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators. ACM Trans. Design Autom. Electr. Syst. 28(3): 34:1-34:23 (2023) - [j56]Wantong Li, Madison Manley, James Read, Ankit Kaul, Muhannad S. Bakir, Shimeng Yu:
H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention. IEEE Trans. Very Large Scale Integr. Syst. 31(10): 1592-1602 (2023) - 2022
- [j55]Jae Hur, Yuan-Chun Luo, Anni Lu, Tzu-Han Wang, Shaolan Li, Asif Islam Khan, Shimeng Yu:
Nonvolatile Capacitive Crossbar Array for In-Memory Computing. Adv. Intell. Syst. 4(8) (2022) - [j54]Hongwu Jiang, Wantong Li, Shanshi Huang, Stefan Cosemans, Francky Catthoor, Shimeng Yu:
Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators. IEEE Des. Test 39(2): 48-55 (2022) - [j53]Yandong Luo, Sourav Dutta, Ankit Kaul, Sung Kyu Lim, Muhannad S. Bakir, Suman Datta, Shimeng Yu:
A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 445-457 (2022) - [j52]Wonbo Shim, Shimeng Yu:
GP3D: 3D NAND Based In-Memory Graph Processing Accelerator. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 500-507 (2022) - [j51]Georgios Ch. Sirakoulis, Alon Ascoli, Ronald Tetzlaff, Shimeng Yu:
Guest Editorial Memristive Circuits and Systems for Edge-Computing Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4): 717-722 (2022) - [j50]Wantong Li, James Read, Hongwu Jiang, Shimeng Yu:
MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4): 835-845 (2022) - [j49]Yandong Luo, Panni Wang, Shimeng Yu:
Accelerating On-Chip Training with Ferroelectric-Based Hybrid Precision Synapse. ACM J. Emerg. Technol. Comput. Syst. 18(2): 35:1-35:20 (2022) - [j48]Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Yen-Lin Chung, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Hongwu Jiang, Shanshi Huang, Sih-Han Li, Shyh-Shyuan Sheu, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shimeng Yu, Meng-Fan Chang:
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. IEEE J. Solid State Circuits 57(2): 609-624 (2022) - [j47]Wantong Li, Xiaoyu Sun, Shanshi Huang, Hongwu Jiang, Shimeng Yu:
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References. IEEE J. Solid State Circuits 57(9): 2868-2877 (2022) - [j46]Jian Meng, Wonbo Shim, Li Yang, Injune Yeo, Deliang Fan, Shimeng Yu, Jae-sun Seo:
Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference. IEEE Micro 42(1): 89-98 (2022) - [j45]Yandong Luo, Yuan-Chun Luo, Shimeng Yu:
A Ferroelectric-Based Volatile/Non-Volatile Dual-Mode Buffer Memory for Deep Neural Network Accelerators. IEEE Trans. Computers 71(9): 2088-2101 (2022) - [j44]Saurabh Dash, Yandong Luo, Anni Lu, Shimeng Yu, Saibal Mukhopadhyay:
Robust Processing-In-Memory With Multibit ReRAM Using Hessian-Driven Mixed-Precision Computation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1006-1019 (2022) - [j43]Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu:
Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 784-788 (2022) - [j42]Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu:
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices. ACM Trans. Design Autom. Electr. Syst. 27(4): 37:1-37:19 (2022) - 2021
- [j41]Beomseok Kang, Anni Lu, Yun Long, Daehyun Kim, Shimeng Yu, Saibal Mukhopadhyay:
Genetic Algorithm-Based Energy-Aware CNN Quantization for Processing-In-Memory Architecture. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 649-662 (2021) - [j40]Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu:
NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark. Frontiers Artif. Intell. 4: 659060 (2021) - [j39]Bohan Lin, Yachuan Pang, Bin Gao, Jianshi Tang, Dong Wu, Ting-Wei Chang, Wei-En Lin, Xiaoyu Sun, Shimeng Yu, Meng-Fan Chang, He Qian, Huaqiang Wu:
A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source. IEEE J. Solid State Circuits 56(5): 1641-1650 (2021) - [j38]Mohsen Jafarzadeh, Stephen Brooks, Shimeng Yu, Balakrishnan Prabhakaran, Yonas Tadesse:
A wearable sensor vest for social humanoid robots with GPGPU, IoT, and modular software architecture. Robotics Auton. Syst. 139: 103536 (2021) - [j37]Yandong Luo, Shimeng Yu:
AILC: Accelerate On-Chip Incremental Learning With Compute-in-Memory Technology. IEEE Trans. Computers 70(8): 1225-1238 (2021) - [j36]Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu:
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(11): 2306-2319 (2021) - [j35]Shimeng Yu, Wonbo Shim, Xiaochen Peng, Yandong Luo:
RRAM for Compute-in-Memory: From Inference to Training. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2753-2765 (2021) - [j34]Jian Meng, Li Yang, Xiaochen Peng, Shimeng Yu, Deliang Fan, Jae-Sun Seo:
Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1576-1580 (2021) - [j33]Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu:
A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference. ACM Trans. Design Autom. Electr. Syst. 26(6): 45:1-45:18 (2021) - [j32]Gauthaman Murali, Xiaoyu Sun, Shimeng Yu, Sung Kyu Lim:
Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 386-396 (2021) - [j31]Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu:
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2027-2039 (2021) - 2020
- [j30]Xiaoming Chen, Kai Ni, Michael T. Niemier, Dayane Reis, Xiaoyu Sun, Panni Wang, Suman Datta, Xiaobo Sharon Hu, Xunzhao Yin, Matthew Jerry, Shimeng Yu, Ann Franchesca Laguna:
The Impact of Ferroelectric FETs on Digital and Analog Circuits and Architectures. IEEE Des. Test 37(1): 79-99 (2020) - [j29]Xin Si, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun:
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. IEEE J. Solid State Circuits 55(1): 189-202 (2020) - [j28]Hongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu:
CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays. IEEE Trans. Computers 69(7): 944-954 (2020) - [j27]Yandong Luo, Shimeng Yu:
Accelerating Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses. IEEE Trans. Computers 69(8): 1113-1127 (2020) - [j26]Xiaochen Peng, Rui Liu, Shimeng Yu:
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(4): 1333-1343 (2020) - [j25]Anni Lu, Xiaochen Peng, Yandong Luo, Shimeng Yu:
Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint. IEEE Trans. Very Large Scale Integr. Syst. 28(9): 1945-1952 (2020) - 2019
- [j24]Pai-Yu Chen, Shimeng Yu:
Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures. IEEE Des. Test 36(3): 31-38 (2019) - [j23]Manqing Mao, Xiaochen Peng, Rui Liu, Jingtao Li, Shimeng Yu, Chaitali Chakrabarti:
MAX2: An ReRAM-Based Neural Network Accelerator That Maximizes Data Reuse and Area Utilization. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(2): 398-410 (2019) - [j22]Xiaoyu Sun, Shimeng Yu:
Impact of Non-Ideal Characteristics of Resistive Synaptic Devices on Implementing Convolutional Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(3): 570-579 (2019) - [j21]Shihui Yin, Jae-sun Seo, Yulhwa Kim, Xu Han, Hugh J. Barnaby, Shimeng Yu, Yandong Luo, Wangxin He, Xiaoyu Sun, Jae-Joon Kim:
Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. IEEE Micro 39(6): 54-63 (2019) - [j20]Xin Si, Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xiaoyu Sun, Rui Liu, Shimeng Yu, Hiroyuki Yamauchi, Qiang Li, Meng-Fan Chang:
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4172-4185 (2019) - [j19]Panni Wang, Feng Xu, Bo Wang, Bin Gao, Huaqiang Wu, He Qian, Shimeng Yu:
Three-Dimensional nand Flash for Vector-Matrix Multiplication. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 988-991 (2019) - [j18]Jiyong Woo, Shimeng Yu:
Impact of Selector Devices in Analog RRAM-Based Crossbar Arrays for Inference and Training of Neuromorphic System. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2205-2212 (2019) - 2018
- [j17]Shimeng Yu:
Neuro-Inspired Computing With Emerging Nonvolatile Memorys. Proc. IEEE 106(2): 260-285 (2018) - [j16]Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang:
MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 1009-1022 (2018) - [j15]Pai-Yu Chen, Xiaochen Peng, Shimeng Yu:
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3067-3080 (2018) - [j14]Rui Liu, Pai-Yu Chen, Xiaochen Peng, Shimeng Yu:
X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3459-3468 (2018) - [j13]Manqing Mao, Shimeng Yu, Chaitali Chakrabarti:
Design and Analysis of Energy-Efficient and Reliable 3-D ReRAM Cross-Point Array System. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1290-1300 (2018) - 2017
- [j12]Zihan Xu, Steven Skorheim, Ming Tu, Visar Berisha, Shimeng Yu, Jae-sun Seo, Maxim Bazhenov, Yu Cao:
Improving efficiency in sparse learning with the feedforward inhibitory motif. Neurocomputing 267: 141-151 (2017) - [j11]Wenchao Qian, Pai-Yu Chen, Robert Karam, Ligang Gao, Swarup Bhunia, Shimeng Yu:
Energy-Efficient Adaptive Computing With Multifunctional Memory. IEEE Trans. Circuits Syst. II Express Briefs 64-II(2): 191-195 (2017) - [j10]Manqing Mao, Pai-Yu Chen, Shimeng Yu, Chaitali Chakrabarti:
A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1611-1621 (2017) - [j9]Xiaoyu Sun, Rui Liu, Yi-Ju Chen, Hsiao-Yun Chiu, Wei-Hao Chen, Meng-Fan Chang, Shimeng Yu:
Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2962-2965 (2017) - [j8]Amr M. S. Tosson, Shimeng Yu, Mohab H. Anis, Lan Wei:
A Study of the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-Based Neuromorphic Systems. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3125-3137 (2017) - 2016
- [j7]Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Optimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniques. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 352-363 (2016) - [j6]Lixue Xia, Peng Gu, Boxun Li, Tianqi Tang, Xiling Yin, Wenqin Huangfu, Shimeng Yu, Yu Cao, Yu Wang, Huazhong Yang:
Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication. J. Comput. Sci. Technol. 31(1): 3-19 (2016) - [j5]Pai-Yu Chen, Ligang Gao, Shimeng Yu:
Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning. IEEE Trans. Multi Scale Comput. Syst. 2(4): 257-264 (2016) - [j4]Pai-Yu Chen, Zhiwei Li, Shimeng Yu:
Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3460-3467 (2016) - 2015
- [j3]Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo:
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 194-204 (2015) - [j2]Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie:
Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design. ACM Trans. Design Autom. Electr. Syst. 20(4): 63:1-63:21 (2015) - 2012
- [j1]H.-S. Philip Wong, Heng-Yuan Lee, Shimeng Yu, Yu-Sheng Chen, Yi Wu, Pang-Shiu Chen, Byoungil Lee, Frederick T. Chen, Ming-Jinn Tsai:
Metal-Oxide RRAM. Proc. IEEE 100(6): 1951-1970 (2012)
Conference and Workshop Papers
- 2024
- [c123]Janak Sharda, Po-Kai Hsu, Shimeng Yu:
Accelerator Design using 3D Stacked Capacitorless DRAM for Large Language Models. AICAS 2024: 487-491 - [c122]Yuan-Chun Luo, James Read, Anni Lu, Shimeng Yu:
A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators. ASPDAC 2024: 159-164 - [c121]Junmo Lee, Sunbin Deng, Jungyoun Kwak, Minji Shon, Suman Datta, Shimeng Yu:
Optimization of Backside of Silicon-Compatible High Voltage Superlattice Capacitor for 12V-to-6V On-Chip Voltage Conversion. DRC 2024: 1-2 - [c120]Dipjyoti Das, Lance Fernandes, Prasanna Venkatesan Ravindran, Taeyoung Song, Chinsung Park, Nashrah Afroze, Mengkun Tian, Hang Chen, Winston Chem, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Shimeng Yu, Suman Datta, Asif Islam Khan:
Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation. IMW 2024: 1-4 - [c119]Tae-Hyeon Kim, Yuan-Chun Luo, Omkar Phadke, James Read, Shimeng Yu:
Engineering nvCap From FEOL to BEOL with Ferroelectric Small-signal Non-destructive Read. IMW 2024: 1-4 - [c118]Omkar Phadke, Halid Mulaosmanovic, Stefan Dünkel, Sven Beyer, Shimeng Yu:
Reliability Assesement of Ferroelectric nvCAP for Small-Signal Capacitive Read-Out. IRPS 2024: 1-5 - [c117]Priyankka Gundlapudi Ravikumar, Prasanna Venkatesan Ravindran, Khandker Akif Aabrar, Taeyoung Song, Sharadindu Gopal Kirtania, Dipjyoti Das, Chinsung Park, Nashrah Afroze, Mengkun Tian, Shimeng Yu, Ahmad Ehtesham Islam, Suman Datta, Souvik Mahapatra, Asif Islam Khan:
Comprehensive Time Dependent Dielectric Breakdown (TDDB) Characterization of Ferroelectric Capacitors Under Bipolar Stress Conditions. IRPS 2024: 1-5 - [c116]Jungyoun Kwak, Gihun Choe, Junmo Lee, Shimeng Yu:
Monolithic 3D Transposable 3T Embedded DRAM with Back-end-of-line Oxide Channel Transistor. ISCAS 2024: 1-5 - [c115]Jianwei Jia, Zhenge Jia, Omkar Phadke, Gihun Choe, Yiyu Shi, Shimeng Yu:
A Reconfigurable Bandpass Filter with Ferroelectric Devices for Intracardiac Electrograms Monitoring. MWSCAS 2024: 433-436 - [c114]Janak Sharda, Qiucheng Wu, Shiyu Chang, Shimeng Yu:
Impact of In-Pixel Processing Circuit Non-idealities on Multi-object Tracking Accuracy for Autonomous Driving. MWSCAS 2024: 806-810 - [c113]Suman Datta, E. Sarkar, Khandker Akif Aabrar, Shan Deng, J. Shin, Arijit Raychowdhury, Shimeng Yu, Asif Khan:
Amorphous Oxide Semiconductors for Monolithic 3D Integrated Circuits. VLSI Technology and Circuits 2024: 1-2 - [c112]Sunbin Deng, Jungyoun Kwak, Junmo Lee, Dyutimoy Chakraborty, Jaewon Shin, Omkar Phadke, Sharadindu Gopal Kirtania, Chengyang Zhang, Khandker Akif Aabrar, Shimeng Yu, Suman Datta:
Demonstration of On-Chip Switched-Capacitor DC-DC Converters using BEOL Compatible Oxide Power Transistors and Superlattice MIM Capacitors. VLSI Technology and Circuits 2024: 1-2 - [c111]Ankit Kaul, Madison Manley, James Read, Yandong Luo, Xiaochen Peng, Shimeng Yu, Muhannad S. Bakir:
Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration of Compute In-Memory Accelerators. VLSI Technology and Circuits 2024: 1-2 - [c110]Pruek Vanna-Iampikul, Hang Yang, Jungyoun Kwak, Joyce X. Hu, Amaan Rahman, Nesara Eranna Bethur, Callie Hao, Shimeng Yu, Sung Kyu Lim:
Back-side Design Methodology for Power Delivery Network and Clock Routing. VLSI Technology and Circuits 2024: 1-2 - [c109]C. C. Wang, C. C. Kuo, C. H. Wu, A. Lu, H. Y. Lee, C. F. Hsu, P. J. Tzeng, T. Y. Lee, F. R. Hou, M. H. Chang, S. C. Lai, K. Goto, Shimeng Yu, C. I. Wu, C. T. Lin, Y. M. Lin, X. Y. Bao:
P-type SnO Semiconductor Transistor and Application. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c108]Wantong Li, Junmo Lee, Shimeng Yu:
Optimization Strategies for Digital Compute-in-Memory from Comparative Analysis with Systolic Array. AICAS 2023: 1-5 - [c107]Wantong Li, Xitie Zhang, Junmo Lee, F. Levent Degertekin, Shaolan Li, Shimeng Yu:
Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator. BioCAS 2023: 1-5 - [c106]Wangxin He, Jian Meng, Sujan Kumar Gonugondla, Shimeng Yu, Naresh R. Shanbhag, Jae-sun Seo:
PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration. DATE 2023: 1-6 - [c105]Wantong Li, Yandong Luo, Shimeng Yu:
RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers. DATE 2023: 1-6 - [c104]Minah Lee, Anni Lu, Mandovi Mukherjee, Shimeng Yu, Saibal Mukhopadhyay:
CLUE: Cross-Layer Uncertainty Estimator for Reliable Neural Perception using Processing-in-Memory Accelerators. IJCNN 2023: 1-8 - [c103]Sola Woo, Gihun Choe, Asif Islam Khan, Suman Datta, Shimeng Yu:
Design of Ferroelectric-Metal Field-Effect Transistor for Multi-Level-Cell 3D NAND Flash. IMW 2023: 1-4 - [c102]Omkar Phadke, Khandker Akif Aabrar, Yuan-chun Luo, Sharadindu Gopal Kirtania, Asif Islam Khan, Suman Datta, Shimeng Yu:
Low-Frequency Noise Characteristics of Ferroelectric Field-Effect Transistors. IRPS 2023: 1-4 - [c101]James Read, Wantong Li, Shimeng Yu:
Enabling Long-Term Robustness in RRAM-based Compute-In-Memory Edge Devices. ISCAS 2023: 1-5 - [c100]Po-Kai Hsu, Weihong Xu, Tajana Rosing, Shimeng Yu:
An In-Storage Processing Architecture with 3D NAND Heterogeneous Integration for Spectra Open Modification Search. MEMSYS 2023: 14:1-14:7 - [c99]Jungyoun Kwak, Wantong Li, Shimeng Yu:
A Reconfigurable Monolithic 3D Switched-Capacitor DC-DC Converter with Back-End-of-Line Oxide Channel Transistor. MWSCAS 2023: 336-340 - [c98]Sharadindu Gopal Kirtania, Khandker Akif Aabrar, Asif Islam Khan, Shimeng Yu, Samyak Datta:
Cold-FeFET as Embedded Non-Volatile Memory with Unlimited Cycling Endurance. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c97]Wantong Li, Qiucheng Wu, Janak Sharda, Shiyu Chang, Shimeng Yu:
Temporal Frame Filtering with Near-Pixel Compute for Autonomous Driving. AICAS 2022: 29-32 - [c96]Dong Suk Kang, Shimeng Yu:
Design-Technology Co-optimization for Cryogenic Tensor Processing Unit. APCCAS 2022: 1-4 - [c95]Zheng Wang, Nujhat Tasneem, Hang Chen, Shimeng Yu, Winston Chern, Asif Islam Khan:
Improved Endurance with Electron-Only Switching in Ferroelectric Devices. DRC 2022: 1-2 - [c94]Wantong Li, James Read, Hongwu Jiang, Shimeng Yu:
A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling. ESSCIRC 2022: 101-104 - [c93]Po-Kai Hsu, Shimeng Yu:
In-Memory 3D NAND Flash Hyperdimensional Computing Engine for Energy-Efficient SARS-CoV-2 Genome Sequencing. IMW 2022: 1-4 - [c92]Yandong Luo, Piyush Kumar, Yu-Ching Liao, William Hwang, Fen Xue, Wilman Tsai, Shan X. Wang, Azad Naeemi, Shimeng Yu:
Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators. IMW 2022: 1-4 - [c91]Jian Meng, Injune Yeo, Wonbo Shim, Li Yang, Deliang Fan, Shimeng Yu, Jae-Sun Seo:
Sparse and Robust RRAM-based Efficient In-memory Computing for DNN Inference. IRPS 2022: 3 - [c90]James Read, Wantong Li, Shimeng Yu:
A Method for Reverse Engineering Neural Network Parameters from Compute-in-Memory Accelerators. ISVLSI 2022: 302-307 - [c89]Jungyoun Kwak, Gihun Choe, Shimeng Yu:
A monolithic 3D design technology co-optimization with back-end-of-line oxide channel transistor. NANOARCH 2022: 6:1-6:6 - [c88]Abhishek Khanna, Huacheng Ye, Y. Luo, G. Bajpai, M. San Jose, Wriddhi Chakraborty, Shimeng Yu, Patrick Fay, Suman Datta:
BEOL Compatible Ferroelectric Routers for Run-time Reconfigurable Compute-in-Memory Accelerators. VLSI Technology and Circuits 2022: 240-241 - [c87]Khandker Akif Aabrar, Sharadindu Gopal Kirtania, A. Lu, A. Khanna, Wriddhi Chakraborty, M. San Jose, Shimeng Yu, Suman Datta:
A Thousand State Superlattice(SL) FEFET Analog Weight Cell. VLSI Technology and Circuits 2022: 242-243 - [c86]Hongwu Jiang, Wantong Li, Shanshi Huang, Shimeng Yu:
A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays. VLSI Technology and Circuits 2022: 266-267 - [c85]Gihun Choe, Prasanna Venkatesan Ravindran, Anni Lu, Jae Hur, Maximilian Lederer, André Reck, Sarah Lombardo, Nashrah Afroze, Josh Kacher, Asif Islam Khan, Shimeng Yu:
Machine Learning Assisted Statistical Variation Analysis of Ferroelectric Transistors: From Experimental Metrology to Predictive Modeling. VLSI Technology and Circuits 2022: 336-337 - [c84]Xiao Lyu, Pragya R. Shrestha, Mengwei Si, Panni Wang, Junkang Li, Kin P. Cheung, Shimeng Yu, Peide D. Ye:
Determination of Domain Wall Velocity and Nucleation Time by Switching Dynamics Studies of Ferroelectric Hafnium Zirconium Oxide. VLSI Technology and Circuits 2022: 338-339 - 2021
- [c83]Ankit Kaul, Yandong Luo, Xiaochen Peng, Shimeng Yu, Muhannad S. Bakir:
Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance. 3DIC 2021: 1-5 - [c82]Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu:
NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro. AICAS 2021: 1-4 - [c81]Anni Lu, Xiaochen Peng, Shimeng Yu:
Compute-in-RRAM with Limited On-chip Resources. AICAS 2021: 1-4 - [c80]Wantong Li, Shanshi Huang, Xiaoyu Sun, Hongwu Jiang, Shimeng Yu:
Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security. CICC 2021: 1-2 - [c79]Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu:
A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator. DATE 2021: 932-937 - [c78]Yandong Luo, Yuan-Chun Luo, Shimeng Yu:
A FeRAM based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training. DATE 2021: 1871-1876 - [c77]Boce Lin, Gihun Choe, Jae Hur, Asif Islam Khan, Shimeng Yu, Hua Wang:
Experimental RF Characterization of Ferroelectric Hafnium Zirconium Oxide Material at GHz for Microwave Applications. DRC 2021: 1-2 - [c76]Wantong Li, Xiaoyu Sun, Hongwu Jiang, Shanshi Huang, Shimeng Yu:
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References. ESSCIRC 2021: 79-82 - [c75]Shimeng Yu, Wonbo Shim, Jae Hur, Yuan-chun Luo, Gihun Choe, Wantong Li, Anni Lu, Xiaochen Peng:
Compute-in-Memory: From Device Innovation to 3D System Integration. ESSDERC 2021: 21-28 - [c74]Wantong Li, Xiaoyu Sun, Hongwu Jiang, Shanshi Huang, Shimeng Yu:
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References. ESSDERC 2021: 79-82 - [c73]Jae Hur, Yuan-Chun Luo, Zheng Wang, Wonbo Shim, Asif Islam Khan, Shimeng Yu:
A Technology Path for Scaling Embedded FeRAM to 28nm with 2T1C Structure. IMW 2021: 1-4 - [c72]Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu:
Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing. IMW 2021: 1-4 - [c71]Wangxin He, Wonbo Shim, Shihui Yin, Xiaoyu Sun, Deliang Fan, Shimeng Yu, Jae-sun Seo:
Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing. IRPS 2021: 1-7 - [c70]Wonbo Shim, Jian Meng, Xiaochen Peng, Jae-sun Seo, Shimeng Yu:
Impact of Multilevel Retention Characteristics on RRAM based DNN Inference Engine. IRPS 2021: 1-4 - [c69]Shanshi Huang, Xiaochen Peng, Hongwu Jiang, Yandong Luo, Shimeng Yu:
Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning. ISCAS 2021: 1-5 - [c68]Panni Wang, Xiaochen Peng, Wriddhi Chakraborty, Asif Khan, Suman Datta, Shimeng Yu:
Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator. ISCAS 2021: 1-4 - [c67]Shanshi Huang, Hongwu Jiang, Shimeng Yu:
Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune. NVMSA 2021: 1-6 - 2020
- [c66]Yandong Luo, Shimeng Yu:
Benchmark Non-volatile and Volatile Memory Based Hybrid Precision Synapses for In-situ Deep Neural Network Training. ASP-DAC 2020: 422-427 - [c65]Shimeng Yu, Xiaoyu Sun, Xiaochen Peng, Shanshi Huang:
Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects. CICC 2020: 1-4 - [c64]Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu:
A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. DAC 2020: 1-6 - [c63]Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu:
Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories. DATE 2020: 1025-1030 - [c62]Yuan-Chun Luo, Jae Hur, Panni Wang, Asif Islam Khan, Shimeng Yu:
Modeling Multi-states in Ferroelectric Tunnel Junction. DRC 2020: 1-2 - [c61]Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu:
XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption. ICCAD 2020: 77:1-77:6 - [c60]Wonbo Shim, Yandong Luo, Jae-sun Seo, Shimeng Yu:
Impact of Read Disturb on Multilevel RRAM based Inference Engine: Experiments and Model Prediction. IRPS 2020: 1-5 - [c59]Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Shimeng Yu:
MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture. ISCAS 2020: 1-5 - [c58]Yandong Luo, Xiaochen Peng, Ryan Hatcher, Titash Rakshit, Jorge Kittl, Mark S. Rodder, Jae-Sun Seo, Shimeng Yu:
A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out. ISCAS 2020: 1-5 - [c57]Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Zhixiao Zhang, Hongwu Jiang, Shanshi Huang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shyh-Shyuan Sheu, Sih-Han Li, Heng-Yuan Lee, Shih-Chieh Chang, Shimeng Yu, Meng-Fan Chang:
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. ISSCC 2020: 240-242 - [c56]Wonbo Shim, Hongwu Jiang, Xiaochen Peng, Shimeng Yu:
Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine. MEMSYS 2020: 77-85 - [c55]Hongwu Jiang, Rui Liu, Shimeng Yu:
8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator. MWSCAS 2020: 257-260 - [c54]Shimeng Yu:
Compute-in-Memory for AI: From Inference to Training. VLSI-DAT 2020: 1 - 2019
- [c53]Wenqiang Zhang, Xiaochen Peng, Huaqiang Wu, Bin Gao, Hu He, Youhui Zhang, Shimeng Yu, He Qian:
Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis. DAC 2019: 140 - [c52]Yandong Luo, Xiaochen Peng, Shimeng Yu:
MLP+NeuroSimV3.0: Improving On-chip Learning Performance with Device to Algorithm Optimizations. ICONS 2019: 1:1-1:7 - [c51]Zhilu Ye, Rui Liu, Hugh J. Barnaby, Shimeng Yu:
Evaluation of Single Event Effects in SRAM and RRAM Based Neuromorphic Computing System for Inference. IRPS 2019: 1-4 - [c50]Xiaochen Peng, Rui Liu, Shimeng Yu:
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture. ISCAS 2019: 1-5 - [c49]Jiyong Woo, Shimeng Yu:
Design Space Exploration of Ovonic Threshold Switch (OTS) for Sub-Threshold Read Operation in Cross-Point Memory Arrays. ISCAS 2019: 1-5 - [c48]Xin Si, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang:
A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. ISSCC 2019: 396-398 - [c47]Yachun Pang, Bin Gao, Dong Wu, Shengyu Yi, Qi Liu, Wei-Hao Chen, Ting-Wei Chang, Wei-En Lin, Xiaoyu Sun, Shimeng Yu, He Qian, Meng-Fan Chang, Huaqiang Wu:
A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10-6 Native Bit Error Rate. ISSCC 2019: 402-404 - [c46]Xiaochen Peng, Minkyu Kim, Xiaoyu Sun, Shihui Yin, Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Jae-sun Seo, Shimeng Yu:
Inference engine benchmarking across technological platforms from CMOS to RRAM. MEMSYS 2019: 471-479 - [c45]Hongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu:
CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training. MEMSYS 2019: 490-496 - [c44]Panni Wang, Zheng Wang, Nujhat Tasneem, Jar Hur, Asif Islam Khan, Shimeng Yu:
Investigating Dynamic Minor Loop of Ferroelectric Capacitor. NVMTS 2019: 1-4 - 2018
- [c43]Xiaochen Peng, Shimeng Yu:
Benchmark of RRAM based Architectures for Dot-Product Computation. APCCAS 2018: 378-381 - [c42]Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu:
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. ASP-DAC 2018: 574-579 - [c41]Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu:
Parallelizing SRAM arrays with customized bit-cell for binary neural networks. DAC 2018: 21:1-21:6 - [c40]Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu:
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. DATE 2018: 1423-1428 - [c39]Pai-Yu Chen, Shimeng Yu:
Reliability perspective of resistive synaptic devices on the neuromorphic system performance. IRPS 2018: 5 - [c38]Jiyong Woo, Xiaochen Peng, Shimeng Yu:
Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic Computing. ISCAS 2018: 1-4 - [c37]Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang:
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. ISSCC 2018: 496-498 - [c36]Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo, Chaitali Chakrabarti:
A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks. SiPS 2018: 13-18 - [c35]Manqing Mao, Xiaoyu Sun, Xiaochen Peng, Shimeng Yu, Chaitali Chakrabarti:
A Versatile ReRAM-based Accelerator for Convolutional Neural Networks. SiPS 2018: 211-216 - [c34]Shimeng Yu, Chenchen Liu, Wujie Wen, Yiran Chen:
Special session on reliability and vulnerability of neuromorphic computing systems. VTS 2018: 1 - 2017
- [c33]Rui Liu, Huaqiang Wu, Yachun Pang, He Qian, Shimeng Yu:
Extending 1kb RRAM array from weak PUF to strong PUF by employment of SHA module. AsianHOST 2017: 67-72 - [c32]Amr M. S. Tosson, Shimeng Yu, Mohab H. Anis, Lan Wei:
1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays. ASICON 2017: 12-15 - [c31]Rui Liu, Heng-Yuan Lee, Shimeng Yu:
Analyzing inference robustness of RRAM synaptic array in low-precision neural network. ESSDERC 2017: 18-21 - [c30]Amr M. S. Tosson, Shimeng Yu, Mohab H. Anis, Lan Wei:
Mitigating the Effect of Reliability Soft-errors of RRAM Devices on the Performance of RRAM-based Neuromorphic Systems. ACM Great Lakes Symposium on VLSI 2017: 53-58 - [c29]Rui Liu, Pai-Yu Chen, Shimeng Yu:
Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array. ISCAS 2017: 1-4 - [c28]Amr M. S. Tosson, Shimeng Yu, Mohab H. Anis, Lan Wei:
Analysis of RRAM Reliability Soft-Errors on the Performance of RRAM-Based Neuromorphic Systems. ISVLSI 2017: 62-67 - 2016
- [c27]Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang:
MNSIM: Simulation platform for memristor-based neuromorphic computing system. DATE 2016: 469-474 - [c26]Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, Swarup Bhunia:
Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM. ACM Great Lakes Symposium on VLSI 2016: 299-304 - [c25]Rui Liu, Huaqiang Wu, Yachun Pang, He Qian, Shimeng Yu:
A highly reliable and tamper-resistant RRAM PUF: Design and experimental validation. HOST 2016: 13-18 - [c24]Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu:
Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing. ICCAD 2016: 15 - [c23]Pai-Yu Chen, Shimeng Yu:
Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing. ISCAS 2016: 2310-2313 - [c22]Ayush Shrivastava, Pai-Yu Chen, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Design of a reliable RRAM-based PUF for compact hardware security primitives. ISCAS 2016: 2326-2329 - 2015
- [c21]Peng Gu, Boxun Li, Tianqi Tang, Shimeng Yu, Yu Cao, Yu Wang, Huazhong Yang:
Technological exploration of RRAM crossbar array for matrix-vector multiplication. ASP-DAC 2015: 106-111 - [c20]Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu:
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. DATE 2015: 854-859 - [c19]Shimeng Yu, Yu Cao:
On-chip Sparse Learning with Resistive Cross-point Array Architecture. ACM Great Lakes Symposium on VLSI 2015: 195-197 - [c18]Pai-Yu Chen, Runchen Fang, Rui Liu, Chaitali Chakrabarti, Yu Cao, Shimeng Yu:
Exploiting resistive cross-point array for compact design of physical unclonable function. HOST 2015: 26-31 - [c17]Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie:
Overcoming the challenges of crossbar resistive memory architectures. HPCA 2015: 476-488 - [c16]Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu:
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. ICCAD 2015: 194-199 - [c15]Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings. ICCD 2015: 359-366 - [c14]Jinfeng Kang, Bin Gao, Peng Huang, Lifeng Liu, Xiaoyan Liu, H. Y. Yu, Shimeng Yu, H.-S. Philip Wong:
RRAM based synaptic devices for neuromorphic visual systems. DSP 2015: 1219-1222 - [c13]Scott Zuloaga, Rui Liu, Pai-Yu Chen, Shimeng Yu:
Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design. ISCAS 2015: 193-196 - [c12]Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Programming strategies to improve energy efficiency and reliability of ReRAM memory systems. SiPS 2015: 1-6 - 2014
- [c11]Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie:
Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture. ASP-DAC 2014: 825-830 - [c10]Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Deepak Kadetotad, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Jae-sun Seo, Yu Cao:
Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. BICA 2014: 126-133 - [c9]Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo:
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. BioCAS 2014: 536-539 - [c8]Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie:
Reliability-aware cross-point resistive memory design. ACM Great Lakes Symposium on VLSI 2014: 145-150 - [c7]Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie:
Architecting 3D vertical resistive memory for next-generation storage systems. ICCAD 2014: 55-62 - [c6]Jinfeng Kang, Bin Gao, Bing Chen, Peng Huang, Feifei Zhang, Xiaoyan Liu, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong, Shimeng Yu:
Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture. ISCAS 2014: 417-420 - [c5]Shimeng Yu, Yexin Deng, Bin Gao, Peng Huang, Bing Chen, Xiaoyan Liu, Jinfeng Kang, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong:
Design guidelines for 3D RRAM cross-point architecture. ISCAS 2014: 421-424 - [c4]Shimeng Yu:
Orientation classification by a winner-take-all network with oxide RRAM based synaptic devices. ISCAS 2014: 1058-1061 - [c3]Shimeng Yu, Duygu Kuzum, H.-S. Philip Wong:
Design considerations of synaptic device for neuromorphic computing. ISCAS 2014: 1062-1065 - [c2]Shimeng Yu:
Overview of resistive switching memory (RRAM) switching mechanism and device modeling. ISCAS 2014: 2017-2020 - [c1]Jinghua Yang, Niranjan Kulkarni, Shimeng Yu, Sarma B. K. Vrudhula:
Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. NANOARCH 2014: 39-44
Informal and Other Publications
- 2024
- [i12]Zijian Zhao, Sola Woo, Khandker Akif Aabrar, Sharadindu Gopal Kirtania, Zhouhang Jiang, Shan Deng, Yi Xiao, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Steven Soss, Sven Beyer, Rajiv V. Joshi, Scott Meninger, Mohamed Mohamed, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Vijaykrishnan Narayanan, Suman Datta, Shimeng Yu, Kai Ni:
Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate. CoRR abs/2403.04981 (2024) - [i11]S. J. Ben Yoo, Luis El Srouji, Suman Datta, Shimeng Yu, Jean Anne C. Incorvia, Alberto Salleo, Volker J. Sorger, Juejun Hu, Lionel C. Kimerling, Kristofer Bouchard, Joy Geng, Rishidev Chaudhuri, Charan Ranganath, Randall C. O'Reilly:
Towards Reverse-Engineering the Brain: Brain-Derived Neuromorphic Computing Approach with Photonic, Electronic, and Ionic Dynamicity in 3D integrated circuits. CoRR abs/2403.19724 (2024) - [i10]Wei-Hsing Huang, Jianwei Jia, Yuyao Kong, Faaiq Waqar, Tai-Hao Wen, Meng-Fan Chang, Shimeng Yu:
Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference. CoRR abs/2409.11418 (2024) - 2023
- [i9]Weihong Xu, Junwei Chen, Po-Kai Hsu, Jaeyoung Kang, Minxuan Zhou, Sumukh Pinge, Shimeng Yu, Tajana Rosing:
Proxima: Near-storage Acceleration for Graph-based Approximate Nearest Neighbor Search in 3D NAND. CoRR abs/2312.04257 (2023) - 2022
- [i8]Mohsen Jafarzadeh, Stephen Brooks, Shimeng Yu, Balakrishnan Prabhakaran, Yonas Tadesse:
A wearable sensor vest for social humanoid robots with GPGPU, IoT, and modular software architecture. CoRR abs/2201.02192 (2022) - 2021
- [i7]Shanshi Huang, Hongwu Jiang, Shimeng Yu:
Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune. CoRR abs/2104.06377 (2021) - 2020
- [i6]Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu:
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training. CoRR abs/2003.06471 (2020) - [i5]Sho Ko, Shimeng Yu:
SMART Paths for Latency Reduction in ReRAM Processing-In-Memory Architecture for CNN Inference. CoRR abs/2004.04865 (2020) - 2019
- [i4]Fuxi Cai, Suhas Kumar, Thomas Van Vaerenbergh, Rui Liu, Can Li, Shimeng Yu, Qiangfei Xia, J. Joshua Yang, Raymond G. Beausoleil, Wei Lu, John Paul Strachan:
Harnessing Intrinsic Noise in Memristor Hopfield Neural Networks for Combinatorial Optimization. CoRR abs/1903.11194 (2019) - [i3]Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo:
High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS. CoRR abs/1909.07514 (2019) - 2018
- [i2]Chetan Singh Thakur, Jamal Molin, Gert Cauwenberghs, Giacomo Indiveri, Kundan Kumar, Ning Qiao, Johannes Schemmel, Runchun Wang, Elisabetta Chicca, Jennifer Olson Hasler, Jae-sun Seo, Shimeng Yu, Yu Cao, André van Schaik, Ralph Etienne-Cummings:
Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain. CoRR abs/1805.08932 (2018) - 2015
- [i1]Sukru Burc Eryilmaz, Duygu Kuzum, Shimeng Yu, H.-S. Philip Wong:
Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures. CoRR abs/1512.08030 (2015)
Coauthor Index
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