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"15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM ..."

Jian-Wei Su et al. (2020)

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DOI: 10.1109/ISSCC19947.2020.9062949

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

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  - conf/isscc/SuSCCHTLLLWZJHL20
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  - https://dblp.org/rec/conf/isscc/SuSCCHTLLLWZJHL20
Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Zhixiao Zhang, Hongwu Jiang, Shanshi Huang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shyh-Shyuan Sheu, Sih-Han Li, Heng-Yuan Lee, Shih-Chieh Chang, Shimeng Yu, Meng-Fan Chang:
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. ISSCC 2020: 240-242

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