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Yulhwa Kim
Person information
- affiliation: Pohang University of Science and Technology, South Korea
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2020 – today
- 2024
- [c14]Jaeyong Jang, Yulhwa Kim, Juheun Lee, Jae-Joon Kim:
FIGNA: Integer Unit-Based Accelerator Design for FP-INT GEMM Preserving Numerical Accuracy. HPCA 2024: 760-773 - [i6]Hyesung Jeon, Yulhwa Kim, Jae-Joon Kim:
L4Q: Parameter Efficient Quantization-Aware Training on Large Language Models via LoRA-wise LSQ. CoRR abs/2402.04902 (2024) - [i5]Jiwon Song, Kyungseok Oh, Taesu Kim, Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim:
SLEB: Streamlining LLMs through Redundancy Verification and Elimination of Transformer Blocks. CoRR abs/2402.09025 (2024) - [i4]Dongwon Jo, Taesu Kim, Yulhwa Kim, Jae-Joon Kim:
Mixture of Scales: Memory-Efficient Token-Adaptive Binarization for Large Language Models. CoRR abs/2406.12311 (2024) - 2023
- [c13]Yulhwa Kim, Jaeyong Jang, Jehun Lee, Jihoon Park, Jeonghoon Kim, Byeongwook Kim, Baeseong Park, Se Jung Kwon, Dongsoo Lee, Jae-Joon Kim:
Winning Both the Accuracy of Floating Point Activation and the Simplicity of Integer Arithmetic. ICLR 2023 - [c12]Yulhwa Kim, Dongwon Jo, Hyesung Jeon, Taesu Kim, Daehyun Ahn, Hyungjun Kim, Jae-Joon Kim:
Leveraging Early-Stage Robustness in Diffusion Models for Efficient and High-Quality Image Synthesis. NeurIPS 2023 - [i3]Jiwoong Choi, Minkyu Kim, Daehyun Ahn, Taesu Kim, Yulhwa Kim, Dongwon Jo, Hyesung Jeon, Jae-Joon Kim, Hyungjun Kim:
Squeezing Large-Scale Diffusion Models for Mobile. CoRR abs/2307.01193 (2023) - 2022
- [j4]Yulhwa Kim
, Hyungjun Kim
, Jae-Joon Kim
:
Extreme Partial-Sum Quantization for Analog Computing-In-Memory Neural Network Accelerators. ACM J. Emerg. Technol. Comput. Syst. 18(4): 75:1-75:19 (2022) - [j3]Sungju Ryu
, Hyungjun Kim
, Wooseok Yi, Eunhwan Kim
, Yulhwa Kim
, Taesu Kim
, Jae-Joon Kim
:
BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks. IEEE J. Solid State Circuits 57(6): 1924-1935 (2022) - 2021
- [j2]Daehyun Ahn
, Hyunmyung Oh, Hyungjun Kim
, Yulhwa Kim
, Jae-Joon Kim
:
Maximizing Parallel Activation of Word-Lines in MRAM-Based Binary Neural Network Accelerators. IEEE Access 9: 141961-141969 (2021) - [c11]Hyunmyung Oh, Hyungjun Kim, Nameun Kang, Yulhwa Kim
, Jihoon Park, Jae-Joon Kim:
Single RRAM Cell-based In-Memory Accelerator Architecture for Binary Neural Networks. AICAS 2021: 1-4 - [c10]Hyunmyung Oh, Hyungjun Kim, Daehyun Ahn, Jihoon Park, Yulhwa Kim
, Inhwan Lee, Jae-Joon Kim:
Energy-efficient charge sharing-based 8T2C SRAM in-memory accelerator for binary neural networks in 28nm CMOS. A-SSCC 2021: 1-3 - [c9]Yulhwa Kim
, Hyungjun Kim, Jihoon Park, Hyunmyung Oh, Jae-Joon Kim:
Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs. DATE 2021: 856-861 - 2020
- [c8]Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jongeun Koo, Eunhwan Kim
, Yulhwa Kim
, Taesu Kim, Jae-Joon Kim:
A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS. CICC 2020: 1-4 - [c7]Hyungjun Kim, Yulhwa Kim
, Sungju Ryu, Jae-Joon Kim:
Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead. DAC 2020: 1-6 - [c6]Naebeom Park, Yulhwa Kim
, Daehyun Ahn, Taesu Kim, Jae-Joon Kim:
Time-step interleaved weight reuse for LSTM neural network computing. ISLPED 2020: 13-18
2010 – 2019
- 2019
- [j1]Shihui Yin, Jae-sun Seo, Yulhwa Kim
, Xu Han, Hugh J. Barnaby, Shimeng Yu
, Yandong Luo, Wangxin He, Xiaoyu Sun, Jae-Joon Kim:
Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. IEEE Micro 39(6): 54-63 (2019) - [c5]Hyungjun Kim, Yulhwa Kim
, Jae-Joon Kim:
In-memory batch-normalization for resistive memory based binary neural network hardware. ASP-DAC 2019: 645-650 - [c4]Wooseok Yi, Yulhwa Kim
, Jae-Joon Kim:
Effect of Device Variation on Mapping Binary Neural Network to Memristor Crossbar Array. DATE 2019: 320-323 - [c3]Jinseok Kim, Jongeun Koo, Taesu Kim, Yulhwa Kim
, Hyungjun Kim, Seunghyun Yoo, Jae-Joon Kim:
Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array. VLSI Circuits 2019: 118- - [i2]Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim:
BitSplit-Net: Multi-bit Deep Neural Network with Bitwise Activation Function. CoRR abs/1903.09807 (2019) - 2018
- [c2]Jinseok Kim, Yulhwa Kim
, Sungho Kim, Jae-Joon Kim:
Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay. ISLPED 2018: 3:1-3:6 - [c1]Yulhwa Kim
, Hyungjun Kim, Daehyun Ahn, Jae-Joon Kim:
Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array. ISLPED 2018: 41:1-41:6 - [i1]Yulhwa Kim, Hyungjun Kim, Jae-Joon Kim:
Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators. CoRR abs/1811.02187 (2018)
Coauthor Index
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last updated on 2024-07-25 20:23 CEST by the dblp team
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