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ORCIDIMW 2023: Monterey, CA, USA
- IEEE International Memory Workshop, IMW 2023, Monterey, CA, USA, May 21-24, 2023. IEEE 2023, ISBN 978-1-6654-7459-7
Session 1: Keynotes
- Sun Il Shim, Jaehoon Jang, Jaihyuk Song:
Trends and Future Challenges of 3D NAND Flash Memory. 1-4 - Alessandro Grossi, Matteo Coppetta, Stefano Aresu, Andreas Kux, Thomas Kern, Robert Strenz:
28nm Data Memory with Embedded RRAM Technology in Automotive Microcontrollers. 1-4 - Jeongdong Choe:
Recent Technology Insights on STT-MRAM: Structure, Materials, and Process Integration. 1-4
Session 2: 3D Nand I
- Gianluca Nicosia, Niccolò Righetti, Yingda Dong:
Distributed Cycling in Charge Trap-Based 3D NAND Arrays: Model and Qualification Tests Implications. 1-4 - Soochan Chung, Dong-Hyeon Ko, Joonsung Lim, Kyungmoon Kim, Sejie Takaki, Yujeong Seo, Byoungil Lee, Sejun Park, Jaeduk Lee, Kyungyoon Noh, Sujin Ahn, Sunghoi Hur:
Process Improvements for 7th Generation 1Tb Quad-Level Cell 3D NAND Flash Memory in Mass Production. 1-4 - Suhwan Lim, Samki Kim, Changhee Lee, Hyeongwon Choi, Nambin Kim, Jaehun Jung, Hanvit Yang, Tae-Hun Kim, Junhee Lim, Daewon Ha, Sunghoi Hur, Jae-hoon Jang, Yu-Gyun Shin, Jaihyuk Song:
Improvement of GIDL-assisted Erase by using Surrounded BL PAD Structure for VNAND. 1-4
Session 3: 3D DRAM & Selectors
- Meng Huang, Shufang Si, Zheng He, Ying Zhou, Sijia Li, Hong Wang, Jinying Liu, Dongsheng Xie, Mengmeng Yang, Kang You, Chris Choi, Yi Tang, Xiaojie Li, Shibing Qian, Xiaodong Yang, Long Hou, Weiping Bai, Zhongming Liu, Yanzhe Tang, Qiong Wu, Yanqin Wang, Tao Dou
, Jake Kim, Guilei Wang, Jie Baisp, Adachi Takao, Chao Zhao, Abraham Yoo:
A 3D Stackable 1T1C DRAM: Architecture, Process Integration and Circuit Simulation. 1-4 - Daohuan Feng, Yi Jiang, Yunsong Qiu, Yuhong Zheng, Harry Kim, Jaewoo Kim, Jian Chu, Guangsu Shao, Yucheng Liao, Chen Yang, Minrui Hu, Wenli Zhao, Linjiang Xia, Jianfeng Xiao, Di Ma, Yuan Cheng, Xiangbo Kong, Chao Lin, Tianming Li, Yongjie Li, Jingheng Meng, Kai Shao, Yan Wang, Xiaoan Yang, Xiang Liu, Qinghua Han, Huiming Li, Yanzhe Tang, Mingde Liu, Eric Wu, Xiaoping Li, Renrui Huang, Mingtang Zhang, Long Hou, Xuan Pan, Xinwen Jin, Shuiping Zhao, Dh Han, Ted Park, Deyuan Xiao, Chao Zhao, Abraham Yoo:
Vertical Channel Transistor (VCT) as Access Transistor for Future 4F2 DRAM Architecture. 1-4 - Wei-Chen Chen, Hang-Ting Lue, Tzu-Hsuan Hsu, Keh-Chung Wang, Chih-Yuan Lu:
A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device. 1-4
Session 4: Ferro
- Konrad Seidel, David Lehninger, Franz Müller, Yannick Raffel, Ayse Sünbül, Ricardo Revello, Raik Hoffmann, Sourav De, Thomas Kämpfe, Maximilian Lederer:
Hafnium oxide-based Ferroelectric Memories: Are we ready for Application? 1-4 - Zhuo Chen, Nicolo Ronchi, Amey Walke, Kaustuv Banerjee, Mihaela Ioana Popovici, Kostantine Katcko, Geert Van den Bosch, Maarten Rosmeulen, Valeri Afanas'ev, Jan Van Houdt:
Improved MW of IGZO-channel FeFET by Reading Scheme Optimization and Interfacial Engineering. 1-4 - Laurent Breuil, Mihaela Popovici, J. Stiers, Antonio Arreghini, S. Ramesh, G. Van den Bosch, Jan Van Houdt, Maarten Rosmeulen:
Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NAND. 1-4 - J. Laguerre, Marc Bocquet, Olivier Billoint, S. Martin, Jean Coignus, Catherine Carabasse, Thomas Magis, T. Dewolf, François Andrieu, Laurent Grenouillet:
Memory Window in Si: HfO2 FeRAM arrays: Performance Improvement and Extrapolation at Advanced Nodes. 1-4
Session 5: 3D Nand II
- Song-Hyeon Kuk, Jae-Hoon Han, Bong Ho Kim, Junpyo Kim, Sang-Hyeon Kim:
Proposal of P-Channel FE NAND with High Drain Current and Feasible Disturbance for Next Generation 3D NAND. 1-4 - Biswajit Ray, Matchima Buddhanoy, Mondol Anik Kumar:
Towards Improving Ionizing Radiation Tolerance of 3-D NAND Flash Memory. 1-4 - Andrew Bicksler, Carmine Miccoli, Srinath Venkatesan:
Physical Model and Characteristics of 3D NAND Memory Cell Metastability Issues under High Temperature Stress. 1-4 - S. Rachidi, S. Ramesh, L. Breuil, Z. Tao, Devin Verreck, G. L. Donadio, Antonio Arreghini, G. Van den Bosch, Maarten Rosmeulen:
Enabling 3D NAND Trench Cells for Scaled Flash Memories. 1-4
Session 6: Systems, STT & RRAM
- Kazuma Hasegawa, Yuta Aiba, Xu Li, Hitomi Tanaka, Takayuki Miyazaki, Hideko Mukaida, Masaru Koyanagi, Masayuki Miura, Tomoya Sanuki:
Low Power and Thermal Throttling-less SSD with In-Package Boost Converter for 1000-WL Layer 3D Flash Memory. 1-4 - Donato Francesco Falcone, Stephan Menzel, Tommaso Stecconi, Antonio La Porta, Ludovico Carraria-Martinotti, Bert Jan Offrein, Valeria Bragaglia:
Physical modeling and design rules of analog Conductive Metal Oxide-HfO2 ReRAM. 1-4 - Antonino Conte, Francesco Tomaiuolo, Marco Ruta, Andrea Redaelli, Franck Arnaud, Thomas Jouanneau, Christian Boccaccio, Olivier Weber:
An 18nm ePCM with BJT selector NVM design for advanced microcontroller applications. 1-4 - Astha Khandelwal, Rajesh Chopdekar, Akash Surampalli, Kaushal Tiwari, Naveen Negi, Alan Kalitsov, Lei Wan, Jordan A. Katine, Derek Stewart, Tiffany S. Santos, Yen-Lin Huang, Ramamoorthy Ramesh, Bhagwati Prasad:
Voltage Control of Magnetism: Low-Power Spintronics. 1-4
Session 7: Neuromorphic/In-Mem
- Subhali Subhechha, Stefan Cosemans, Attilio Belmonte, Nouredine Rassoul, Shamin Houshmand Sharifi, Peter Debacker, Diederik Verkest, Romain Delhougne, Gouri Sankar Kar:
Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays. 1-4 - Franz Müller, Sourav De, Maximilian Lederer, Raik Hoffmann, Ricardo Olivo, Thomas Kämpfe, Konrad Seidel, Tarek Ali, Halid Mulaosmanovic, Stefan Dünkel, Johannes Müller, Sven Beyer, Gerald Gerlach:
Multi-Level Operation of Ferroelectric FET Memory Arrays for Compute-In-Memory Applications. 1-4 - Po-Hao Tseng, Tian-Cig Bo, Yu-Hsuan Lin, Yu-Chao Lin, Jhe-Yi Liao, Feng-Ming Lee, Yu-Yu Lin, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
SLC and MLC In-Memory-Approximate-Search Solutions in Commercial 48-layer and 96-layer 3D-NAND Flash Memories. 1-4 - Siddharth Rao, Kaiming Cai, Giacomo Talmelli, Nathali Franchina-Vergel, Ward Janssens, Hubert Hody, Farrukh Yasin, Kurt Wostyn, Sebastien Couet:
Spin-orbit torque MRAM for ultrafast cache and neuromorphic computing applications. 1-4
Session 8: 3D Processing
- Pradeep Subrahmanyan, Wonjae Lee, Jeff Lischer, Ram Karur, Olga Kucher, Stan Todorov, Adaeze Osonkie:
Overlay Control in HAR device integration. 1-4 - Zhijun Chen, Fred Fishburn, Chang Seok Kang, Sony Varghese, Bala Haran:
Materials Enabled Memory Scaling and New Architectures. 1-4
Posters Session
- Viktor Markov, Gilles Festes, Louisa Schneider, Steven Lemke, Serguei Jourba, Alexander Kotov:
Effect of High-Temperature Bake on RTN Statistics in Floating Gate Flash Memory Arrays. 1-4 - Bastien Giraud, S. Ricavy, Yasser Moursy, C. Laffond, I. Sever, Valentin Gherman, M. Pezzin, Florent Lepin, M. Diallo, K. Zenati, S. Dumas, M. Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noël, A. Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas:
Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro. 1-4 - Xianzhou Shao, Junshuai Chai, Min Liao, Jiahui Duan, Fengbin Tian, Xiaoyu Ke, Xiaoqing Sun, Hao Xu, Jinjuan Xiang, Xiaolei Wang, Wenwu Wang:
Comprehensive Study of Endurance Fatigue in the Scaled Si FeFET by in-situ Vth Measurement and Endurance Enhancement Strategy. 1-4 - Noboru Shibata, Hironori Uchikawa, Taira Shibuya, Kenri Nakai, Kosuke Yanagidaira, Hirofumi Inoue:
7-Bit/2Cell (X3.5), 9-Bit/2Cell (X4.5) NAND Flash Memory: Half Bit technology. 1-4 - Z. Asher Bai, Yixian Wang, Lixue Liu, Xi Zhang, Feng Yuan, Junsheng Meng, Zhongming Liu, Js Jeon, James Cho, Blacksmith Wu, Huihui Li, Guilei Wang, Chao Zhao, Kanyu Cao:
Dielectric Relaxation Performance of DRAM Storage Capacitors and Ways of Improvement. 1-4 - Takuto Nishimura, Yuya Ichikawa, Akira Goda, Naoko Misawa, Chihiro Matsui, Ken Takeuchi:
Stochastic Computing-based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of Non-volatile Memory Error and Defect Tolerance. 1-4 - Yuri Tkachev, Steven Lemke, Louisa Schneider, Gilles Festes, Parviz Ghazavi:
Analog Tuning of Floating-Gate Cells with Sub-Elementary Charge Accuracy for In-Memory Computing Applications. 1-4 - David Lehninger, Ayse Sünbül, Ricardo Olivo, Thomas Kämpfe, Konrad Seidel, Maximilian Lederer:
Ferroelectric HfO2/ZrO2 Superlattices with Improved Leakage at Bias and Temperature Stress. 1-4 - Nicola Lepri, P. Gibertini, Piergiulio Mannocci, A. Pirovano, I. Tortorelli, Paolo Fantini, Daniele Ielmini:
In-memory neural network accelerator based on phase change memory (PCM) with one-selector/one-resistor (1S1R) structure operated in the subthreshold regime. 1-4 - Vivek Parmar, Sandeep Kaur Kingra, Deepak Verma, Digamber Pandey, Giuseppe Piccolboni, Alessandro Bricalli, Amir Regev, Gabriel Pares, Laurent Grenouillet, Jean-François Nodin, Manan Suri:
Demonstration of SMT-reflow Immune and SCA-resilient PUF on 28nm RRAM device array. 1-4 - Sola Woo, Gihun Choe, Asif Islam Khan, Suman Datta, Shimeng Yu:
Design of Ferroelectric-Metal Field-Effect Transistor for Multi-Level-Cell 3D NAND Flash. 1-4 - Yasuhiro Taniguchi, Shoji Yoshida, Teruhiko Egashira, ChihBin Kuo, YiYang Shie, YuChun Wang, ChenYu Huang, Tsuyoshi Tamatsu, Keiji Okamoto, Masanobu Hishiki, Yasushi Sasaki, Fukuo Owada, Nobuhiko Ito, Yutaka Shinagawa, ChihMing Kuo, Satoshi Noda, Toshikazu Matsui, Kosuke Okuyama:
SONOS Embedded Flash IP Using Trap-Depth-Controlled SiN Film Enabling Data Retention more than 10 years at 200°C. 1-4 - Wei-Chih Chien, E. K. Lai, L. Buzi, C. W. Cheng, C. W. Yeh, A. Ray, Lynne M. Gignac, N. Gong, H. Y. Cheng, A. Grun, D. Y. Lee, W. Kim, A. Majumdar, Douglas M. Bishop, Robert L. Bruce, D. Daudelin, H. Y. Ho, M. J. BrightSky, H. L. Lung:
A Comprehensive Study on the Pillar Size of OTS-PCM Memory with an Optimized Process and Scaling Trends Down to Sub-10 nm for SCM Applications. 1-4 - Tobias Ziegler, Leon Brackmann, Tyler Hennen, Christopher Bengel, Stephan Menzel, Dirk J. Wouters:
Eliminating Capacitive Sneak Paths in Associative Capacitive Networks based on Complementary Resistive Switches for In-Memory Computing. 1-4
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