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ORCIDISVLSI 2004: Tampa, Florida, USA
- 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA. IEEE Computer Society 2004, ISBN 0-7695-2097-9
Regular Papers
Emerging Trends in VLSI Systems
- Michael T. Niemier, Peter M. Kogge:
The "4-Diamond Circuit" - A Minimally Complex Nano-Scale Computational Building Block in QCA. 3-10 - Benjamin Gojman, Eric Rachlin, John E. Savage:
Decoding of Stochastically Assembled Nanoarrays. 11-18 - A. J. KleinOsowski, David J. Lilja:
The NanoBox Project: Exploring Fabrics of Self-Correcting Logic Blocks for High Defect Rate Molecular Device Technologies. 19-24 - Debayan Bhaduri, Sandeep K. Shukla:
NANOLAB: A Tool for Evaluating Reliability of Defect-Tolerant Nano Architectures. 25-31 - Lun Li, Mitchell A. Thornton, Stephen A. Szygenda:
A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking. 32-38
System Level Design
- Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha:
System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. 39-45 - Matthew Pirretti, Greg M. Link, Richard R. Brooks
, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Fault Tolerant Algorithms for Network-On-Chip Interconnect. 46-51 - Suryaprasad Jayadevappa, Ravi Shankar, Imad Mahgoub:
A Comparative Study of Modeling at Different Levels of Abstraction in System on Chip Designs: A Case Study. 52-60
System-on-a-Chip Design
- Kristian Hildingsson, Tughrul Arslan, Ahmet T. Erdogan:
Energy Evaluation Methodology for Platform Based System-on-Chip Design. 61-68 - Alain Lopez, Denis Deschacht:
Comparison between Different Data Buses Configurations. 69-76
Advanced VLSI Design
- Theo Theocharides, Greg M. Link, Eric J. Swankoski, Narayanan Vijaykrishnan, Mary Jane Irwin, Herman Schmit:
Evaluating Alternative Implementations for LDPC Decoder Check Node Function. 77-82 - Alireza Hodjat, Ingrid Verbauwhede:
Minimum Area Cost for a 30 to 70 Gbits/s AES Processor. 83-88 - Earl E. Swartzlander Jr.:
A Review of Large Parallel Counter Designs. 89-98 - María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida:
Behavioural Scheduling to Balance the Bit-Level Computational Effort. 99-104 - Mahadevan Gomathisankaran, Akhilesh Tyagi:
WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays. 105-114
VLSI Circuits and Systems
- Walid Elgharbawy, Magdy A. Bayoumi:
New Bulk Dynamic Threshold NMOS Schemes for Low-Energy Subthreshold Domino-Like Circui. 115-120 - Adam Strak, Hannu Tenhunen:
Suppression of Jitter Effects in A/D Converters through Sigma-Delta Sampling. 121-126 - Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis:
Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. 127-134
Low Power VLSI System Design
- Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou:
Experimental Evaluation of Resonant Clock Distribution. 135-140 - Peiyi Zhao, Pradeep Kumar Golconda, C. Archana, Magdy A. Bayoumi:
A Double-Edge Implicit-Pulsed Level Convert Flip-Flop. 141-144 - Joohee Kim, Conrad H. Ziesler:
Fixed-Load Energy Recovery Memory for Low Power. 145-150 - W. Rhett Davis, Ambarish M. Sule, Hao Hua:
Multi-Parameter Power Minimization of Synthesized Datapaths. 151-157 - Shu-Shin Chin, Sangjin Hong, Suhwan Kim:
Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units. 158-166
Novel Test Techniques
- Mihir A. Shah, Janak H. Patel:
Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs. 167-172 - Chunsheng Liu, Kumar N. Dwarakanath, Krishnendu Chakrabarty, Ronald D. Blanton:
Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST. 173-178 - Makoto Sugihara, Kazuaki J. Murakami, Yusuke Matsunaga:
Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. 179-186
Physical Design, Synthesis and Optimization
- Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui:
Control and Data Flow Graph Extraction for High-Level Synthesis. 187-192 - Hao Li, Wai-Kei Mak, Srinivas Katkoori:
Force-Directed Performance-Driven Placement Algorithm for FPGAs. 193-198 - Sankalp Kallakuri, Alex Doboli, Simona Doboli:
Stochastic Modeling Based Environment for Synthesis and Comparison of Bus Arbitration Policies. 199-206
Poster Papers
- Ghanshyam Nayak, Tejasvi Das, T. M. Rao, P. R. Mukund:
DREAM: A Chip-Package Co-Design Tool for RF-Mixed Signal Systems. 207-210 - Krzysztof Iniewski, Marek Syrzycki:
Low Power 2.5 Gb/s Serializer for SOC Applications. 211-212 - Jie Long, Jo Yi Foo, Robert J. Weber:
A 2.4 GHz Low-Power Low-Phase-Noise CMOS LC VCO. 213-214 - Indrajit Atluri, Tughrul Arslan:
Reconfigurability-Power Trade-Offs in Turbo Decoder Design and Implementation. 215-217 - Erik J. Mentze, Kevin M. Buck, Herbert L. Hess, David Cox, Mohammad M. Mojarradi:
A Low Voltage to High Voltage Level Shifter in a Low Voltage, 0.25 µm, PD SOI Process. 218-221 - Abdsamad Benkrid, Khaled Benkrid, Danny Crookes:
Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. 222-225 - Ahmet T. Erdogan, Tughrul Arslan:
Low Power FIR Filter Implementations Based on Coefficient Ordering Algorithm. 226-228 - S. Sukhsawas, Khaled Benkrid:
A High-Level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAs. 229-232 - Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao:
64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. 233-236 - Sophie Bouchoux, El-Bay Bourennane, Johel Mitéran, Michel Paindavoine:
Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA. 237-238 - Lerong Cheng, William N. N. Hung, Guowu Yang, Xiaoyu Song:
Congestion Estimation for 3D Routing. 239-240 - Hiren D. Patel, Sandeep K. Shukla:
Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models. 241-242 - Weisheng Chong, Masanori Hariyama, Michitaka Kameyama:
Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. 243-248 - Sangjin Hong, Shu-Shin Chin:
Incorporating Power Reduction Mechanism in Arithmetic Core Design. 249-250 - Robert D. Kenney, Michael J. Schulte:
Multioperand Decimal Addition. 251-253 - Abdel Ejnioui, Abdelhalim Alsharqawi:
Pipeline Design Based on Self-Resetting Stage Logic. 254-257 - Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama:
Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure. 258-259 - Chandramouli Gopalakrishnan, Srinivas Katkoori:
Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths. 260-261 - Arindam Mukherjee:
On the Reduction of Simultaneous Switching in SoCs. 262-263 - Nattawut Thepayasuwan, Alex Doboli:
OSIRIS: Automated Synthesis of Flat and Hierarchical Bus Architectures for Deep Submicron Systems on Chip. 264-265 - Peter Zipf, Claude Stötzler, Manfred Glesner:
A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture. 266-267 - Harpreet S. Narula, John G. Harris:
Integrated VLSI Potentiostat for Cyclic Voltammetry in Electrolytic Reactions. 268-270 - Rajarshi Mukherjee, Alex K. Jones, Prithviraj Banerjee:
Handling Data Streams while Compiling C Programs onto Hardware. 271-272 - Shankar Krithivasan, Michael J. Schulte, John Glossner:
A Subword-Parallel Multiplication and Sum-of-Squares Unit. 273-274 - Troy D. Townsend, Peter Celinski, Said F. Al-Sarawi, Michael J. Liebelt:
Hybrid Parallel Counters - Domino and Threshold Logic. 275-276 - Peter-Michael Seidel, Kenneth Fazel:
Two-Dimensional Folding Strategies for Improved Layouts of Cyclic Shifters. 277-278 - Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
A Memory Aware High Level Synthesis Tool . 279-280 - Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos:
Scan Cell Ordering for Low Power BIST. 281-284 - Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos:
An Efficient Test Vector Ordering Method for Low Power Testing. 285-288 - Bassam Shaer:
Concurrent Pseudo-Exhaustive Testing of Combinational VLSI Circuits. 289-290 - Chandrasekar Rajagopal, Adrián Núñez-Aldana:
CMOS Analog Programmable Logic Array. 291-292 - Sotirios Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni:
Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications . 293-296 - John D. Thompson, Nandini Karra, Michael J. Schulte:
A 64-bit Decimal Floating-Point Adder. 297-298 - Nick Iliev, James E. Stine, Nathan Jachimiec:
Parallel Programmable Finite Field GF(2m) Multipliers. 299-302 - Magesh Sadasivam, Sangjin Hong:
Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined Dataflow. 303-304 - Wei Zhang:
Compiler-Directed Data Cache Leakage Reduction. 305-306 - Venu G. Gudise, Ganesh K. Venayagamoorthy:
FPGA Placement and Routing Using Particle Swarm Optimization. 307-308 - Abdel Ejnioui, Abdelkader Rhiati:
A Reconfigurable Memory Management Core for Java Applications. 309-312 - Krishnan Srinivasan, Vijay Ramamurthi, Karam S. Chatha:
A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder. 313-316 - Christian Panis, Ulrich Hirnschrott, Andreas Krall, Gunther Laure, Wolfgang Lazian, Jari Nurmi:
FSEL - Selective Predicated Execution for a Configurable DSP Core. 317-320 - Yuan Li, John G. Harris:
A Spiking Recurrent Neural Network. 321-322
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