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ORCIDASAP 1992: Berkeley, CA, USA
- Application Specific Array Processors, ASAP 1992, Proceedings of the International Conference on, Berkeley, CA, USA, 4-7 August, 1992. IEEE 1992, ISBN 0-8186-2967-3
- Jürgen Teich, Lothar Thiele:
A transformative approach to the partitioning of processor arrays. 4-20 - Phu Hoang, Jan M. Rabaey:
Hierarchical scheduling of DSP programs onto multiprocessors for maximum throughput. 21-36 - Alain Darte, Leonid Khachiyan, Yves Robert:
Linear scheduling is close to optimality. 37-46 - Yin-Tsung Hwang, Yu Hen Hu:
On systolic mapping of multi-stage algorithms. 47-61 - Bharadwaj S. Amrutur, Rajeev Joshi, Narendra K. Karmarkar:
A projective geometry architecture for scientific computation. 64-80 - Glenn Jennings:
On cycle borrowing analyses for interconnected chips driven by clocks having different but commensurable speeds. 81-88 - Matthias Sauer, Ernst G. Bernard, Josef A. Nossek:
On partitioning of multistage algorithms and design of intermediate memories. 89-101 - Jacob Levison, Ichiro Kuroda, Takao Nishitani:
A reconfigurable processor array with routing LSIs and general purpose DSPs. 102-116 - Shiv Prakash, Alice C. Parker:
Synthesis of application-specific multiprocessor systems including memory components. 118-132 - D. C. Chen, Lisa M. Guerra, E. H. Ng, Miodrag Potkonjak, D. P. Schultz, Jan M. Rabaey:
An integrated system for rapid prototyping of high performance algorithm specific data paths. 134-148 - Wayne P. Burleson, Bongjin Jung:
ARREST: an interactive graphic analysis tool for VLSI arrays. 149-162 - Miodrag Potkonjak, Jan M. Rabaey:
Pipelining: just another transformation. 163-175 - Krste Asanovic, James Beck, Brian Kingsbury, Phil Kohn, Nelson Morgan, John Wawrzynek:
SPERT: a VLIW/SIMD microprocessor for artificial neural network computations. 178-190 - Robert Michael Owens, Mary Jane Irwin, Thomas P. Kelliher, Mohan Vishwanath, Raminder Singh Bajwa:
Implementing a family of high performance, micrograined architectures. 191-205 - Michael Murray, James B. Burr, David G. Stork, Ming-Tak Leung, Kan Boonyanit, Gregory J. Wolff, Allen M. Peterson:
Deterministic Boltzmann machine VLSI can be scaled using multi-chip modules. 206-217 - Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin:
Discrete wavelet transforms in VLSI. 218-229 - Stephen E. McQuillan, John V. McCanny:
Algorithms and architectures for high performance recursive filtering. 230-244 - Y. S. Wu:
On metrics of 'super performance' [signal processing systems]. 248-256 - Earl E. Swartzlander Jr.:
Advanced technology for improved signal processor efficiency. 257-268 - Joseph B. Evans, Bede Liu:
Some low power implementations of DSP algorithms. 269-276 - Charles M. Rader:
MUSE-a systolic array for adaptive nulling with 64 degrees of freedom, using Givens transformations and wafer scale integration. 277-291 - T. E. Curtis:
Heterogeneous digital signal processing systems for sonar. 294-302 - Hans Habereder, R. Loyd Harrison:
Constant capacity signal flow signal processor architecture benchmark. 303-315 - Richard R. Shively, Les J. Wu:
Application and packaging of the AT&T DSP3 parallel signal processor. 316-326 - Anton Gunzinger, Urs A. Müller, Walter Scott, Bernhard Bäumle, Peter Kohler, Walter Guggenbühl:
Architecture and realization of a multi signal processor system. 327-340 - Stan Knight, Danny Chin, Herb Taylor, Joseph E. Peters:
The Sarnoff Engine: a massively parallel computer for high definition system simulation. 342-356 - Herbert Dawid, Heinrich Meyr:
High speed bit-level pipelined architectures for redundant CORDIC implementation. 358-372 - Olaf J. Joeressen, Martin Vaupel, Heinrich Meyr:
High-speed VLSI architectures for soft-output Viterbi decoding. 373-384 - Heonchul Park, Viktor K. Prasanna, Cho-Li Wang:
An architecture for tree search based vector quantization for single chip implementation. 385-399 - Mahib Rahman, David G. Meyer:
A systolic array chip for robot inverse dynamics computation. 400-414 - Tanguy Risset:
A method to synthesize modular systolic arrays with local broadcast facility. 415-428 - Flavio Lorenzelli, Kung Yao, Tony F. Chan, Per Christian Hansen:
A systolic rank revealing QR algorithm. 430-444 - Stephan Olariu, James L. Schwing, Jingyuan Zhang:
Interval-related problems on reconfigurable meshes. 445-455 - Kuninobo Tanno, Toshihiro Takeda, Susumu Horoguchi:
A parallel sorting algorithm on an eight-neighbor processor array. 456-468 - Patrick Fitzpatrick, Colin C. Murphy:
Fault tolerant matrix triangularization and solution of linear systems of equations. 469-480 - Ravi K. Kolagotla, Shu-sun Yu, Joseph F. JáJá:
Systolic architectures for finite-state vector quantization. 481-495 - Jaime Moreno, Mario Medina:
Matrix computations in arrays of DSPs. 496-510 - Dinh Lê, Milos D. Ercegovac, Tomás Lang, Jaime H. Moreno:
MAMACG: a tool for automatic mapping of matrix algorithms onto mesh array computational graphs. 511-525 - Amar Mukherjee:
Determining longest common subsequences of two sequences on a linear array of processors. 526-537 - Werner Pöchmüller, Andreas König, Manfred Glesner:
Associative information processing: algorithms and system. 538-550 - Emmanuel D. Frimout, Johannes N. Driessen, Ed F. Deprettere:
Parallel architecture for a pel-recursive motion estimation algorithm. 551-558 - Wonyong Sung, Sanjit K. Mitra, Ki-Il Kum:
Mapping locally recursive SEGs upon a multiprocessor system in a ring network. 560-573 - Wayne W. C. Luk:
Transformation techniques for serial array design. 574-588 - Harry Printz:
Compilation of narrowband spectral detection systems for linear MIMD machines. 589-603 - Richard Hughey:
Programming systolic arrays. 604-618 - Alvaro Suárez, José M. Llabería, Agustín Fernández:
Scheduling partitions in systolic algorithms. 619-633 - Kumar N. Ganapathy, Benjamin W. Wah:
Optimal design of lower dimensional processor arrays for uniform recurrences. 636-648 - Prashanth Kuchibhotla, Bhaskar D. Rao:
Efficient scheduling methods for partitioned systolic algorithms. 649-663 - Duen-Jeng Wang, Yu Hen Hu:
Fully static multiprocessor realization for real-time recursive DSP algorithms. 664-678 - Sebastian Ritz, Matthias Pankert, Heinrich Meyr:
High level software synthesis for signal processing systems. 679-693
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