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"Fast multiplier bit-product matrix reduction using bit-ordering and parity ..."

Ben C. Drerup, Earl E. Swartzlander Jr. (1994)

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DOI: 10.1007/BF02409401

access: closed

type: Journal Article

metadata version: 2020-05-20

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Ben C. Drerup, Earl E. Swartzlander Jr.:
Fast multiplier bit-product matrix reduction using bit-ordering and parity generation. J. VLSI Signal Process. 7(3): 249-257 (1994)

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