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Thomas A. Ziaja
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2010 – 2019
- 2012
- [j2]Manish K. Shah, Robert T. Golla, Greg Grohoski, Paul J. Jordan, Jama Barreh, Jeffrey Brooks, Mark Greenberg, Gideon Levinsky, Mark Luttrell, Christopher Olson, Zeid Samoail, Matt Smittle, Thomas A. Ziaja:
Sparc T4: A Dynamically Threaded Server-on-a-Chip. IEEE Micro 32(2): 8-19 (2012)
2000 – 2009
- 2009
- [c8]Thomas A. Ziaja, Poh J. Tan:
Efficient Array Characterization in the UltraSPARC T2. VTS 2009: 3-8 - 2008
- [c7]Liang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen:
Transition Test on UltraSPARC- T2 Microprocessor. ITC 2008: 1-10 - 2007
- [c6]Robert F. Molyneaux, Thomas A. Ziaja, Hong Kim, Shahryar Aryani, Sungbae Hwang, Alex Hsieh:
Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip. ITC 2007: 1-8 - 2002
- [c5]Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar:
A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors. ITC 2002: 726-735 - 2001
- [c4]Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar:
Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. ICCD 2001: 526-529
1990 – 1999
- 1999
- [c3]Thomas A. Ziaja:
Using LSSD to test modules at the board level. ITC 1999: 163-170 - 1996
- [c2]Thomas A. Ziaja, Earl E. Swartzlander Jr.:
Comprehensive Modeling of VLSI Test. DFT 1996: 159-167 - 1995
- [c1]Thomas A. Ziaja, Earl E. Swartzlander Jr.:
Characterization and analysis of errors in circuit test. DFT 1995: 261-268 - 1994
- [j1]Thomas A. Ziaja, Earl E. Swartzlander Jr.:
Boundary scan in board manufacturing. J. Electron. Test. 5(2-3): 263-268 (1994)
Coauthor Index
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