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ORCID15th IEEE Symposium on Computer Arithmetic 2001: Vail, Colorado, USA
- 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA. IEEE Computer Society 2001, ISBN 0-7695-1150-3
Keynote Speech
- Ruby B. Lee:
Computer Arithmetic-A Processor Architect's Perspective. 3-
Binary Strings in Computer Arithmetic
- Martin S. Schmookler, Kevin J. Nowka
:
Leading Zero Anticipation and Detection-A Comparison of Methods. 7-12 - Tomás Lang, Jean-Michel Muller:
Bounds on Runs of Zeros and Ones for Algebraic Functions. 13-
Multiplication and Exponentiation
- Peter-Michael Seidel, Lee D. McFearin, David W. Matula:
Binary Multiplication Radix-32 and Radix-256. 23-32 - K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte:
Analysis of Column Compression Multipliers. 33-39 - José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller:
Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree. 40-
Cryptography
- Jean-Claude Bajard, Laurent-Stéphane Didier, Peter Kornerup:
Modular Multiplication and Base Extensions in Residue Number Systems. 59-65 - M. Anwarul Hasan:
Efficient Computation of Multiplicative Inverses for Cryptographic Applications. 66-72 - Braden Phillips:
Optimised Squaring of Long Integers Using Precomputed Partial Products. 73-
Division and Square Root
- Tomás Lang, Elisardo Antelo:
Correctly Rounded Reciprocal Square-Root by Digit Recurrence and Radix-4 Implementation. 83-93 - Naofumi Takagi:
A Hardware Algorithm for Computing Reciprocal Square Root. 94-100 - David W. Matula:
Improved Table Lookup Algorithms for Postscaled Division. 101-
Elementary Functions and Rounding
- Vincent Lefèvre, Jean-Michel Muller:
Worst Cases for Correct Rounding of the Elementary Functions in Double Precision. 111-118 - Lee D. McFearin, David W. Matula:
Generation and Analysis of Hard to Round Cases for Binary Floating Point Division. 119-127 - Florent de Dinechin, Arnaud Tisserand:
Some Improvements on Multipartite Table Methods . 128-135 - Jun Cao, Belle W. Y. Wei, Jie Cheng:
High-Performance Architectures for Elementary Function Generation. 136-
Number Systems
- Michael F. Cowlishaw, Eric M. Schwarz, Ronald M. Smith, Charles F. Webb:
A Decimal Floating-Point Specification. 147-154 - Yozo Hida, Xiaoye S. Li, David H. Bailey:
Algorithms for Quad-Double Precision Floating Point Arithmetic. 155-162 - David R. Lester:
Effective Continued Fractions. 163-
Floating Point Units
- Ajay Naini, Atul Dhablania, Warren James, Debjit Das Sarma:
1-GHz HAL SPARC64 Dual Floating Point Unit with RAS Features. 173-183 - Peter-Michael Seidel, Guy Even:
On the Design of Fast IEEE Floating-Point Adders. 184-194 - Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Moon Key Lee, Sang-Woo Kim:
In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32. 195-
Addition
- Javier D. Bruguera, Tomás Lang:
Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition. 203-210 - Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. 211-217 - Andrew Beaumont-Smith, Cheng-Chew Lim:
Parallel Prefix Adder Design. 218-
Logarithmic Number Systems
- Vassilis Paliouras, Thanos Stouraitis:
Low-Power Properties of the Logarithmic Number System. 229-236 - Mark G. Arnold, Colin D. Walter:
Unrestricted Faithful Rounding is Good Enough for Some LNS Applications. 237-246 - Vassil S. Dimitrov, Jonathan Eskritt, Laurent Imbert, Graham A. Jullien, William C. Miller:
The Use of the Multi-Dimensional Logarithmic Number System in DSP Applications. 247-
On-Line Arithmetic
- Sridhar Rajagopal, Joseph R. Cavallaro:
On-line Arithmetic for Detection in Digital Communication Receivers. 257-265 - Alexandre F. Tenca, Syed Ubaid Hussaini:
A Design of Radix-2 On-line Division Using LSA Organization. 266-
Addendum: Reprinted Paper from the 14th Computer Arithmetic Symposium
- Simon Knowles:
A Family of Adders. 277-
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