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2010 – 2019
- 2017
[c13]Paul F. Baumeister, B. Rombach, Thorsten Hater, Sabine Griessbach
, L. Hoffmann, Markus Bühler, Dirk Pleiter:
Strategies for Forward Modelling of Infrared Radiative Transfer on GPUs. PARCO 2017: 369-380- 2016
- [c12]Paul F. Baumeister, Marcel Bornemann, Markus Bühler, Thorsten Hater, Benjamin Krill, Dirk Pleiter, Rudolf Zeller:
Addressing Materials Science Challenges Using GPU-accelerated POWER8 Nodes. Euro-Par 2016: 77-89 - [c11]Thorsten Hater, Benedikt Anlauf, Paul F. Baumeister, Markus Bühler, Jiri Kraus, Dirk Pleiter:
Exploring Energy Efficiency for GPU-Accelerated POWER Servers. ISC Workshops 2016: 207-227 - [c10]Alexander Berreth, Benedetto Risio, Markus Bühler, Benedikt Anlauf, Pascal Vezolle:
Performance of the 3D Combustion Simulation Code RECOM®-AIOLOS on IBM® POWER8® Architecture. ISC Workshops 2016: 286-292 - 2011
- [j1]Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Bühler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen D. Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez:
Design methodology for the IBM POWER7 microprocessor. IBM J. Res. Dev. 55(3): 9 (2011) - [c9]Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz:
A theoretical probabilistic simulation framework for dynamic power estimation. ICCAD 2011: 708-715 - [c8]Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz:
A gate sizing method for glitch power reduction. SoCC 2011: 24-29
2000 – 2009
- 2009
- [c7]Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler:
Fast dynamic power estimation considering glitch filtering. SoCC 2009: 361-364 - 2008
- [c6]Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl:
Considering possible opens in non-tree topology wire delay calculation. ACM Great Lakes Symposium on VLSI 2008: 17-22 - 2006
- [c5]Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp:
DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. DATE 2006: 387-392 - [c4]Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller, Sven Peyer, Christian Schulte:
Yield Improvement by Local Wiring Redundancy. ISQED 2006: 473-478
1990 – 1999
- 1999
- [c3]Markus Bühler, Matthias Papesch, K. Kapp, Utz G. Baitinger:
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach. DATE 1999: 459- - 1998
- [c2]K. Kapp, Markus Bühler, D. Dallmann, Utz G. Baitinger:
TESA: Timeparallel Estimation of Switching Activity under a real delay model. ICECS 1998: 233-236 - [c1]Markus Bühler, D. Dallmann, Utz G. Baitinger:
Switching Activity Analysis Using a Set Theoretical Approach. MBMV 1998: 124-130
Coauthor Index
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