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2020 – today
- 2022
- [c93]S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel
:
A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing. ETS 2022: 1-4 - 2021
- [c92]S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel
:
A Plug and Play Digital ABIST Controller for Analog Sensors in Secure Devices. ETS 2021: 1-4 - [c91]Quang-Linh Nguyen, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre:
On Preventing SAT Attack with Decoy Key-Inputs. ISVLSI 2021: 114-119 - 2020
- [c90]Florence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzèrho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea
, T. Vayssade, Arnaud Virazel
:
Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. IOLTS 2020: 1-4 - [c89]Quang-Linh Nguyen, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre:
A Secure Scan Controller for Protecting Logic Locking. IOLTS 2020: 1-6
2010 – 2019
- 2019
- [j26]Emanuele Valea
, Mathieu Da Silva, Giorgio Di Natale
, Marie-Lise Flottes
, Bruno Rouzeyre:
A Survey on Security Threats and Countermeasures in IEEE Test Standards. IEEE Des. Test 36(3): 95-116 (2019) - [j25]Emanuele Valea
, Mathieu Da Silva
, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
Stream vs block ciphers for scan encryption. Microelectron. J. 86: 65-76 (2019) - [j24]Mathieu Da Silva
, Marie-Lise Flottes
, Giorgio Di Natale
, Bruno Rouzeyre:
Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(3): 538-550 (2019) - [c88]Emanuele Valea
, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
Encryption-Based Secure JTAG. DDECS 2019: 1-6 - [c87]Emanuele Valea
, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Sophie Dupuis, Bruno Rouzeyre:
Providing Confidentiality and Integrity in Ultra Low Power IoT Devices. DTIS 2019: 1-6 - [c86]Marc Merandat, Vincent Reynaud, Emanuele Valea
, Jérôme Quévremont, Nicolas Valette, Paolo Maistri, Régis Leveugle, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre, Giorgio Di Natale:
A Comprehensive Approach to a Trusted Test Infrastructure. IVSW 2019: 43-48 - [i2]Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre:
SECCS: SECure Context Saving for IoT Devices. CoRR abs/1903.04314 (2019) - 2018
- [j23]Sophie Dupuis
, Marie-Lise Flottes
, Giorgio Di Natale
, Bruno Rouzeyre:
Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead. IEEE Des. Test 35(2): 73-90 (2018) - [j22]Raphael Andreoni Camponogara Viera
, Jean-Max Dutertre
, Marie-Lise Flottes, Olivier Potin, Giorgio Di Natale, Bruno Rouzeyre, Rodrigo Possamai Bastos
:
Assessing body built-in current sensors for detection of multiple transient faults. Microelectron. Reliab. 88-90: 128-134 (2018) - [c85]Emanuele Valea
, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre:
SI ECCS: SECure context saving for IoT devices. DTIS 2018: 1-2 - [c84]Jean-Max Dutertre
, Vincent Beroulle, Philippe Candelier, Stephan De Castro, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hély, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou
, Bruno Rouzeyre:
Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model. FDTC 2018: 1-6 - [c83]Jean-Max Dutertre
, Vincent Beroulle, Philippe Candelier, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hély
, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou
, Bruno Rouzeyre:
The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks. IOLTS 2018: 214-219 - [c82]Mathieu Da Silva, Emanuele Valea
, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno Rouzeyre:
A New Secure Stream Cipher for Scan Chain Encryption. IVSW 2018: 68-73 - [c81]Mathieu Da Silva, Emanuele Valea
, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno Rouzeyre:
Encryption of test data: which cipher is better? PRIME 2018: 85-88 - 2017
- [c80]Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Paolo Prinetto, Marco Restifo:
Scan chain encryption for the test, diagnosis and debug of secure circuits. ETS 2017: 1-6 - [c79]Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
Experimentations on scan chain encryption with PRESENT. IVSW 2017: 45-50 - [c78]Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre:
Hacking the Control Flow error detection mechanism. IVSW 2017: 51-56 - 2016
- [j21]Stephan De Castro, Jean-Max Dutertre
, Bruno Rouzeyre, Giorgio Di Natale, Marie-Lise Flottes:
Frontside Versus Backside Laser Injection: A Comparative Study. ACM J. Emerg. Technol. Comput. Syst. 13(1): 6:1-6:15 (2016) - [c77]Papa-Sidi Ba, Sophie Dupuis, Palanichamy Manikandan, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique. ISVLSI 2016: 254-259 - [c76]Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
Using outliers to detect stealthy hardware trojan triggering? IVSW 2016: 1-6 - 2015
- [c75]Sophie Dupuis, Papa-Sidi Ba, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
New testing procedure for finding insertion sites of stealthy hardware trojans. DATE 2015: 776-781 - [c74]Marie-Lise Flottes, Sophie Dupuis, Papa-Sidi Ba, Bruno Rouzeyre:
On the limitations of logic testing for detecting Hardware Trojans Horses. DTIS 2015: 1-5 - [c73]Papa-Sidi Ba, Palanichamy Manikandan, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
Hardware Trojan prevention using layout-level design approach. ECCTD 2015: 1-4 - [c72]Marie-Lise Flottes, Joao Azevedo, Giorgio Di Natale, Bruno Rouzeyre:
Session-less based thermal-aware 3D-SIC test scheduling. ETS 2015: 1-2 - [c71]Stephan De Castro, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Jean-Max Dutertre
:
Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits. ISVLSI 2015: 362-367 - [c70]Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Juergen Schloeffel:
3D DFT Challenges and Solutions. ISVLSI 2015: 603-608 - 2014
- [j20]Jean-Max Dutertre
, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Alexandre Sarafianos:
Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS. Microelectron. Reliab. 54(9-10): 2289-2294 (2014) - [j19]Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
:
Test Versus Security: Past and Present. IEEE Trans. Emerg. Top. Comput. 2(1): 50-62 (2014) - [j18]Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 947-951 (2014) - [c69]Jean-Max Dutertre
, Stephan De Castro, Alexandre Sarafianos, Noemie Boher, Bruno Rouzeyre, Mathieu Lisart, Joel Damiens, Philippe Candelier, Marie-Lise Flottes, Giorgio Di Natale:
Laser attacks on integrated circuits: From CMOS to FD-SOI. DTIS 2014: 1-6 - [c68]Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Guillaume Hubert
:
Layout-aware laser fault injection simulation and modeling: From physical level to gate level. DTIS 2014: 1-6 - [c67]Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Customized cell detector for laser-induced-fault detection. IOLTS 2014: 37-42 - [c66]Sophie Dupuis, Papa-Sidi Ba, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans. IOLTS 2014: 49-54 - [c65]Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Juergen Schloeffel:
2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures. ISVLSI 2014: 386-391 - [c64]Régis Leveugle, Paolo Maistri, Pierre Vanhauwaert, Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Athanasios Papadimitriou
, David Hély
, Vincent Beroulle, Guillaume Hubert
, Stephan De Castro, Jean-Max Dutertre
, Alexandre Sarafianos, Noemie Boher, Mathieu Lisart, Joel Damiens, Philippe Candelier, Clément Tavernier:
Laser-induced fault effects in security-dedicated circuits. VLSI-SoC 2014: 1-6 - [c63]Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre
, Marie-Lise Flottes, David Hély
, Guillaume Hubert
, Régis Leveugle, Feng Lu, Paolo Maistri, Athanasios Papadimitriou
, Bruno Rouzeyre, Clément Tavernier, Pierre Vanhauwaert:
Laser-Induced Fault Effects in Security-Dedicated Circuits. VLSI-SoC (Selected Papers) 2014: 220-240 - [c62]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche:
Built-in self-test for manufacturing TSV defects before bonding. VTS 2014: 1-6 - 2013
- [j17]Amitabh Das, Jean DaRolt, Santosh Ghosh, Stefaan Seys, Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
:
Secure JTAG Implementation Using Schnorr Protocol. J. Electron. Test. 29(2): 193-209 (2013) - [j16]Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre:
A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic. J. Electron. Test. 29(3): 331-340 (2013) - [j15]Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis. Inf. Secur. J. A Glob. Perspect. 22(5-6): 226-236 (2013) - [j14]Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Multilevel Ionizing-Induced Transient Fault Simulator. Inf. Secur. J. A Glob. Perspect. 22(5-6): 251-264 (2013) - [j13]Jean-Max Dutertre
, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale:
Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. Microelectron. Reliab. 53(9-11): 1320-1324 (2013) - [j12]Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A novel differential scan attack on advanced DFT structures. ACM Trans. Design Autom. Electr. Syst. 18(4): 58:1-58:22 (2013) - [c61]Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Laser-Induced Fault Simulation. DSD 2013: 609-614 - [c60]Rodrigo Possamai Bastos, Frank Sill Torres
, Jean-Max Dutertre
, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
A bulk built-in sensor for detection of fault attacks. HOST 2013: 51-54 - [c59]Hakim Zimouche, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A BIST method for TSVs pre-bond test. IDT 2013: 1-6 - [c58]Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A smart test controller for scan chains in secure circuits. IOLTS 2013: 228-229 - [c57]Yassine Fkih, Pascal Vivet
, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale:
A 3D IC BIST for pre-bond test of TSVs using ring oscillators. NEWCAS 2013: 1-4 - [c56]Rodrigo Possamai Bastos, Frank Sill Torres
, Jean-Max Dutertre
, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults. PATMOS 2013: 157-163 - 2012
- [j11]Jean DaRolt, Amitabh Das, Santosh Ghosh, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
:
Scan attacks on side-channel and fault attack resistant public-key implementations. J. Cryptogr. Eng. 2(4): 207-219 (2012) - [j10]Rodrigo Possamai Bastos, Frank Sill Torres
, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode. Microelectron. Reliab. 52(9-10): 1781-1786 (2012) - [c55]Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
:
A New Scan Attack on RSA in Presence of Industrial Countermeasures. COSADE 2012: 89-104 - [c54]Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
:
A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures. DFT 2012: 43-48 - [c53]Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
On-chip test comparison for protecting confidential data in secure ICs. ETS 2012: 1 - [c52]Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Are advanced DfT structures sufficient for preventing scan-attacks? VTS 2012: 246-251 - [p1]Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
On Countermeasures Against Fault Attacks on the Advanced Encryption Standard. Fault Analysis in Cryptography 2012: 89-108 - 2011
- [c51]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka, Denis Réal:
Power consumption traces realignment to improve differential power analysis. DDECS 2011: 201-206 - [c50]Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies. DFT 2011: 302-308 - [c49]Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Scan Attacks and Countermeasures in Presence of Scan Response Compactors. ETS 2011: 19-24 - [c48]Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
New security threats against chips containing scan chain structures. HOST 2011: 110 - [c47]Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Timing issues for an efficient use of concurrent error detection codes. LATW 2011: 1-6 - 2010
- [j9]Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre:
Self-Test Techniques for Crypto-Devices. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 329-333 (2010) - [c46]Jerome Di-Battista, Jean-Christophe Courrège, Bruno Rouzeyre, Lionel Torres, Philippe Perdu:
When Failure Analysis Meets Side-Channel Attacks. CHES 2010: 188-202 - [c45]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Ensuring high testability without degrading security: Embedded tutorial on "test and security". DDECS 2010: 6 - [c44]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers. DELTA 2010: 256-261 - [c43]Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Evaluation of concurrent error detection techniques on the Advanced Encryption Standard. ETS 2010: 252 - [c42]Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Evaluation of concurrent error detection techniques on the advanced encryption standard. IOLTS 2010: 223-228
2000 – 2009
- 2009
- [j8]Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre:
A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard. J. Electron. Test. 25(4-5): 269-278 (2009) - [c41]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Execution time reduction of Differential Power Analysis experiments. LATW 2009: 1-5 - 2008
- [c40]M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre:
AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis. DELTA 2008: 314-321 - [c39]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
An Integrated Validation Environment for Differential Power Analysis. DELTA 2008: 527-532 - [c38]Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre:
A Reliable Architecture for the Advanced Encryption Standard. ETS 2008: 13-18 - [c37]Julien Dalmasso, Érika F. Cota, Marie-Lise Flottes, Bruno Rouzeyre:
Improving the Test of NoC-Based SoCs with Help of Compression Schemes. ISVLSI 2008: 139-144 - 2007
- [j7]David Hély
, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre:
Securing Scan Control in Crypto Chips. J. Electron. Test. 23(5): 457-464 (2007) - [c36]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A Novel Parity Bit Scheme for SBox in AES Circuits. DDECS 2007: 267-271 - [c35]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. IOLTS 2007: 57-62 - [c34]Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A Dependable Parallel Architecture for SBoxes. ReCoSoC 2007: 132-137 - [c33]Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre:
Compression-based SoC Test Infrastructures. VLSI-SoC (Selected Papers) 2007: 1-15 - [c32]Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre:
Test data compression and TAM design. VLSI-SoC 2007: 178-183 - [i1]Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre:
Mutation Sampling Technique for the Generation of Structural Test Data. CoRR abs/0710.4802 (2007) - 2006
- [c31]David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre:
A secure scan design methodology. DATE 2006: 1177-1178 - [c30]Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre:
Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains. DELTA 2006: 295-300 - [c29]David Hély
, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre:
Secure Scan Techniques: A Comparison. IOLTS 2006: 119-124 - [c28]David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre:
Scan Pattern Watermarking. LATW 2006: 63-67 - 2005
- [c27]Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre:
Mutation Sampling Technique for the Generation of Structural Test Data. DATE 2005: 1022-1023 - [c26]David Hély
, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre:
Test control for secure scan designs. ETS 2005: 190-195 - 2004
- [j6]Solaiman Rahim, Bruno Rouzeyre, Lionel Torres:
A Flip-Flop Matching Engine to Verify Sequential Optimizations. Comput. Artif. Intell. 23(5): 437-460 (2004) - [c25]Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre:
An Arithmetic Structure for Test Data Horizontal Compression. DATE 2004: 428-435 - [c24]Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre:
On Using Test Vector Differences for Reducing Test Pin Numbers. DELTA 2004: 275-280 - [c23]Ludovic A. Krundel
, Sandeep Kumar Goel, Erik Jan Marinissen
, Marie-Lise Flottes, Bruno Rouzeyre:
User-constrained test architecture design for modular SOC testing. ETS 2004: 80-85 - [c22]David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell:
Scan Design and Secure Chip. IOLTS 2004: 219-226 - 2003
- [c21]Julien Pouget, Erik Larsson
, Zebo Peng, Marie-Lise Flottes, Bruno Rouzeyre:
An efficient approach to SoC wrapper design, TAM configuration and test scheduling. ETW 2003: 51-56 - [c20]Solaiman Rahim, Bruno Rouzeyre, Lionel Torres, Jérôme Rampon:
Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking. HLDVT 2003: 129-134 - 2002
- [j5]Marie-Lise Flottes, Bruno Rouzeyre, Laurent Volpe:
Improving Datapath Testability by Modifying Controller Specification. VLSI Design 15(2): 491-498 (2002) - [c19]Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre:
Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. DATE 2002: 285-289 - [c18]Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre:
A Heuristic for Test Scheduling at System Level. DATE 2002: 1124 - [c17]Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre:
A simple and effective compression scheme for test pins reduction. HLDVT 2002: 165-168 - [e1]Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes:
SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France. IFIP Conference Proceedings 218, Kluwer 2002, ISBN 1-4020-7148-5 [contents] - 2001
- [j4]David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre:
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis. J. Electron. Test. 17(3-4): 331-339 (2001) - [c16]Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre:
Taylor expansion diagrams: a new representation for RTL verification. HLDVT 2001: 70-75 - [c15]Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre:
Functional Test Generation using Constraint Logic Programming. VLSI-SOC 2001: 375-387 - [c14]Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre:
Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme. VLSI-SOC 2001: 401-412 - 2000
- [c13]David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre:
A method for trading off test time, area and fault coverage in datapath BIST synthesis. ETW 2000: 133-139 - [c12]Marie-Lise Flottes, Bruno Rouzeyre, Laurent Volpe:
A controller resynthesis based method for improving datapath testability. ISCAS 2000: 347-350 - [c11]David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre:
BISTing data paths at behavioral level. ITC 2000: 672-680
1990 – 1999
- 1999
- [j3]David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre:
BISTing Datapaths under Heterogeneous Test Schemes. J. Electron. Test. 14(1-2): 115-123 (1999) - 1998
- [c10]Marie-Lise Flottes, R. Pires, Bruno Rouzeyre:
Alleviating DFT Cost Using Testability Driven HLS. Asian Test Symposium 1998: 46-51 - [c9]Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe:
Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. DATE 1998: 921-922 - [c8]Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe:
Low Cost Partial Scan Design: A High Level Synthesis Approach. VTS 1998: 332-340 - 1997
- [j2]Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre:
Improving Testability of Non-Scan Designs during Behavioral Synthesis. J. Electron. Test. 11(1): 29-42 (1997) - [c7]Marie-Lise Flottes, R. Pires, Bruno Rouzeyre:
Analyzing testability from behavioral to RT level. ED&TC 1997: 158-165 - 1995
- [c6]Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre:
High-level synthesis for easy testability. ED&TC 1995: 198-206 - [c5]Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre:
Is High-Level Test Synthesis Just Design for Test? ITC 1995: 294 - 1994
- [c4]Bruno Rouzeyre, D. Dupont, Georges Sagnes:
Component Selection, Scheduling and Control Schemes for High Level Synthesis. EDAC-ETC-EUROASIC 1994: 482-489 - [c3]Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre:
Automatic Synthesis of BISTed Data Paths From High Level Specification. EDAC-ETC-EUROASIC 1994: 591-598 - 1991
- [c2]F. Monteiro, Bruno Rouzeyre, Georges Sagnes:
High level synthesis: a data path partitioning method dedicated to speed enhancement. EURO-DAC 1991: 123-128 - [c1]Gerard Tarroux, Bruno Rouzeyre, Georges Sagnes:
Optimization of micro-controllers by partitioning. EURO-DAC 1991: 368-373
1980 – 1989
- 1989
- [j1]Bruno Rouzeyre, Toufic Ezzedine, Georges Sagnes:
Operators allocation in the silicon compiler SCOOP. Integr. 8(2): 99-109 (1989)
Coauthor Index
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