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2010 – 2019
- 2016
[j7]Chung-Han Chou, Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Chieh Chang, Yung-Tai Chang:
Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1189-1192 (2016)- 2015
- [j6]Shih-Hsu Huang, Hua-Hsin Yeh, Yow-Tyng Nieh:
Clock Period Minimization with Minimum Leakage Power. ACM Trans. Design Autom. Electr. Syst. 21(1): 9:1-9:33 (2015) - 2014
- [c9]Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh:
Leakage-power-aware clock period minimization. DATE 2014: 1-6 - 2013
- [c8]Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou:
Low-power timing closure methodology for ultra-low voltage designs. ICCAD 2013: 697-704
2000 – 2009
- 2009
- [j5]Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh:
Opposite-phase register switching for peak current minimization. ACM Trans. Design Autom. Electr. Syst. 14(1): 14:1-14:29 (2009) - 2007
- [j4]Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu:
Opposite-Phase Clock Tree for Peak Current Reduction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2727-2735 (2007) - [j3]Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh:
A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains. J. Inf. Sci. Eng. 23(6): 1681-1705 (2007) - [j2]Shih-Hsu Huang, Yow-Tyng Nieh:
Clock skew scheduling with race conditions considered. ACM Trans. Design Autom. Electr. Syst. 12(4): 45 (2007) - [c7]Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh:
Clock Period Minimization with Minimum Delay Insertion. DAC 2007: 970-975 - 2006
- [j1]Shih-Hsu Huang, Yow-Tyng Nieh:
Synthesis of nonzero clock skew circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 961-976 (2006) - [c6]Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh:
Fast multi-domain clock skew scheduling for peak current reduction. ASP-DAC 2006: 254-259 - [c5]Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu:
Register binding for clock period minimization. DAC 2006: 439-444 - [c4]Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh:
State re-encoding for peak current minimization. ICCAD 2006: 33-38 - 2005
- [c3]Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu:
Minimizing peak current via opposite-phase clock tree. DAC 2005: 182-185 - [c2]Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu:
Race-condition-aware clock skew scheduling. DAC 2005: 475-478 - 2003
- [c1]Shih-Hsu Huang, Yow-Tyng Nieh:
Clock Period Minimization of Non-Zero Clock Skew Circuits. ICCAD 2003: 809-812
Coauthor Index
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