43. DAC 2006: San Francisco, CA, USA

Session 1: Panel

Session 2: special session: why doesn't my system work?

Session 3: hierarchical synthesis for mixed-signal designs

Session 4: processor and communication centric SOC design

Session 5: practical applications of DFM

DAC technologist panel

Session 7: special session: bridging the system to RTL verification gap

Session 8: leakage, power analysis and optimization

Session 9: MPSOC design methodologies and applications

Session 10: statistical timing analysis


Session 12: Special Session: reliability challenges for 65NM and beyond

Session 13: power grid analysis and design

Session 14: advances in formal solvers

Session 15: gate modeling and model order reduction

Session 16: special session: MPSOC design tools

Session 17: special session - highlights of ISSCC: multimedia

Session 18: buffer insertion

Session 19: testing and validation for timing defects

Session 20: advanced topics in processor and system verification

Session 21: software for real-time applications

Session 22: panel

Session 23: invited session

Session 24: routing

Session 25: the test bin

Session 26: panel

Session 27: low power and ultra-low voltage design

Session 28: high-level exploration and optimization

Session 29: panel design challenges for next-generation multimedia, game and entertainment platforms

Session 30: CAD for FPGAS

Session 31: secure systems

Session 32: logic synthesis I

Session 33: low-power, thermal-aware architectures

Session 34: low power system level design

Session 35: power-constrained design for multimedia

Session 36: electrical and thermal issues in FPGAS

Session 37: special session: beyond low-power design: environmental energy harvesting

Session 38: communication-driven synthesis

Session 39: parallelism and memory optimizations

Session 40: panel

Session 41: nanotubes and nanowires

Session 42: simulation assisted formal verification

Session 43: yield analysis and improvement

Session 44: approaches to soft error mitigation

Session 45: design/technology interaction

Session 46: panel

Session 47: special session: more Moore's law and more than Moore's law

Session 48: formal specification and verification testbench generation

Session 49: analysis and optimization issues in NoC design

Session 50: special session: key technologies for beyond the die

Session 51: analog design and design assistance

Session 52: high-performance simulation of transaction level and dataflow models

Session 53: nano- and bio-chip design

Session 54: logic and sequential synthesis

Session 55: low power circuit design

Session 56: beyond-the-die circuit and system integration

Session 57: new ideas in analog/RF modeling and simulation

Session 58: advanced methods for interconnect extraction, clocks and reliability

Session 59: panel

Session 60: bounded model checking and equivalence verification

Session 61: test response compaction and ATPG

Session 62: placement