43. DAC 2006:
San Francisco, CA, USA Ellen Sentovich (Ed.):
Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006.
ACM 2006, ISBN 1-59593-381-6 Session 1:
Panel
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Session 2:
special session:
why doesn't my system work?
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conf/dac/AbramoviciBDLMM06 export record as
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Session 3:
hierarchical synthesis for mixed-signal designs
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conf/dac/EeckelaertSGSS06 export record as
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Session 4:
processor and communication centric SOC design
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Xinping Zhu ,
Wei Qin :
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery.
53-56
Session 5:
practical applications of DFM
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DAC technologist panel
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Session 7:
special session:
bridging the system to RTL verification gap
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Stuart Swan :
SystemC transaction level models and RTL verification.
90-92
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Session 8:
leakage, power analysis and optimization
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Session 9:
MPSOC design methodologies and applications
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Session 10:
statistical timing analysis
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Panel
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Session 12:
Special Session:
reliability challenges for 65NM and beyond
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Session 13:
power grid analysis and design
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Hao Yu ,
Yiyu Shi ,
Lei He :
Fast analysis of structured power grid by triangularization based structure preserving model order reduction.
205-210
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Session 14:
advances in formal solvers
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Session 15:
gate modeling and model order reduction
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N. Wong ,
C. K. Chu :
A fast passivity test for descriptor systems via structure-preserving transformations of Skew-Hamiltonian/Hamiltonian matrix pencils.
261-266
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Peng Li ,
Weiping Shi :
Model order reduction of linear networks with massive ports via frequency-dependent port packing.
267-272
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Session 16:
special session:
MPSOC design tools
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Grant Martin :
Overview of the MPSoC design challenge.
274-279
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Session 17:
special session - highlights of ISSCC:
multimedia
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conf/dac/PanCHCLCLLHWLLTYMCCPHCH06 Jyh-Shin Pan ,
Hao-Cheng Chen ,
Bing-Yu Hsieh ,
Hong-Ching Chen ,
Roger Lee ,
Ching-Ho Chu ,
Yuan-Chin Liu ,
Chuan Liu ,
Lily Huang ,
Chang-Long Wu ,
Meng-Hsueh Lin ,
Chun-Yiu Lin ,
Shang-Nien Tsai ,
Jenn-Ning Yang ,
Chang-Po Ma ,
Yung Cheng ,
Shu-Hung Chou ,
Hsiu-Chen Peng ,
Peng-Chuan Huang ,
Benjamin Chiu ,
Alex Ho :
A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications.
290-291
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conf/dac/HattoriIIYKSYNYKTHAHTSMYHMYHTYIKMYITAAO06 Toshihiro Hattori ,
Takahiro Irita ,
Masayuki Ito ,
Eiji Yamamoto ,
Hisashi Kato ,
Go Sado ,
Tetsuhiro Yamada ,
Kunihiko Nishiyama ,
Hiroshi Yagi ,
Takao Koike ,
Yoshihiko Tsuchihashi ,
Motoki Higashida ,
Hiroyuki Asano ,
Izumi Hayashibara ,
Ken Tatezawa ,
Yasuhisa Shimazaki ,
Naozumi Morino ,
Yoshihiko Yasu ,
Tadashi Hoshi ,
Yujiro Miyairi ,
Kazumasa Yanagisawa ,
Kenji Hirose ,
Saneaki Tamaki ,
Shinichi Yoshioka ,
Toshifumi Ishii ,
Yusuke Kanno ,
Hiroyuki Mizuno ,
Tetsuya Yamada ,
Naohiko Irie ,
Reiko Tsuchihashi ,
Nobuto Arai ,
Tomohiro Akiyama ,
Koji Ohno :
Hierarchical power distribution and power management scheme for a single chip mobile processor.
292-295
Session 18:
buffer insertion
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Yuantao Peng ,
Xun Liu :
Low-power repeater insertion with both delay and slew rate constraints.
302-307
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Session 19:
testing and validation for timing defects
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Session 20:
advanced topics in processor and system verification
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Alon Gluska :
Practical methods in coverage-oriented verification of the merom microprocessor.
332-337
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Session 21:
software for real-time applications
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Xiangrong Zhou ,
Peter Petrov :
Rapid and low-cost context-switch through embedded processor customization for real-time and control applications.
352-357
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Session 22:
panel
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Session 23:
invited session
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Session 24:
routing
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Session 25:
the test bin
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Session 26:
panel
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Session 27:
low power and ultra-low voltage design
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Hari Ananthan ,
Kaushik Roy :
A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS.
413-418
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Session 28:
high-level exploration and optimization
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Jason Cong ,
Zhiru Zhang :
An efficient and versatile scheduling algorithm based on SDC formulation.
433-438
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Session 29:
panel design challenges for next-generation multimedia, game and entertainment platforms
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Session 30:
CAD for FPGAS
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conf/dac/GopalakrishnanLP06 export record as
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Session 31:
secure systems
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Session 32:
logic synthesis I
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Kuo-Hua Wang :
Exploiting K-Distance Signature for Boolean Matching and G-Symmetry Detection.
516-521
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Session 33:
low-power, thermal-aware architectures
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conf/dac/BurginCHMMSKFF06
Session 34:
low power system level design
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Session 35:
power-constrained design for multimedia
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Session 36:
electrical and thermal issues in FPGAS
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conf/dac/SrinivasanMXVS06
Session 37:
special session:
beyond low-power design:
environmental energy harvesting
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conf/dac/AmirtharajahWCSZ06 export record as
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Session 38:
communication-driven synthesis
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Sujan Pandey ,
Manfred Glesner :
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint.
663-668
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Session 39:
parallelism and memory optimizations
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Session 40:
panel
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Session 41:
nanotubes and nanowires
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Session 42:
simulation assisted formal verification
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Session 43:
yield analysis and improvement
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Jia Wang ,
Hai Zhou :
Optimal jumper insertion for antenna avoidance under ratio upper-bound.
761-766
Session 44:
approaches to soft error mitigation
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conf/dac/Miskov-ZivanovM06 export record as
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Session 45:
design/technology interaction
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Session 46:
panel
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Session 47:
special session:
more Moore's law and more than Moore's law
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Session 48:
formal specification and verification testbench generation
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Session 49:
analysis and optimization issues in NoC design
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Lap-Fai Leung ,
Chi-Ying Tsui :
Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems.
833-838
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Session 50:
special session:
key technologies for beyond the die
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Session 51:
analog design and design assistance
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conf/dac/HammoudaSDTNBAS06 export record as
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Session 52:
high-performance simulation of transaction level and dataflow models
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Session 53:
nano- and bio-chip design
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Session 54:
logic and sequential synthesis
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Chuan Lin ,
Hai Zhou :
An efficient retiming algorithm under setup and hold constraints.
945-950
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Kui Wang ,
Lian Duan ,
Xu Cheng :
ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling.
951-954
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Session 55:
low power circuit design
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Session 56:
beyond-the-die circuit and system integration
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Session 57:
new ideas in analog/RF modeling and simulation
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Ying Wei ,
Alex Doboli :
Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling.
1023-1028
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Guo Yu ,
Peng Li :
Lookup table based simulation and statistical modeling of Sigma-Delta ADCs.
1035-1040
Session 58:
advanced methods for interconnect extraction, clocks and reliability
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Session 59:
panel
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Session 60:
bounded model checking and equivalence verification
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Xiushan Feng ,
Alan J. Hu :
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification.
1063-1068
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conf/dac/PeranandamNRWKR06
Session 61:
test response compaction and ATPG
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Session 62:
placement
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