40. DAC 2003:
Anaheim, CA, USA Real challenges and solutions for validating system-on-chip
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Thomas Schubert :
High level formal verification of next-generation microprocessors.
1-6
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Klaus-Dieter Schubert :
Improvements in functional simulation addressing challenges in large, distributed industry projects.
11-14
Reshaping EDA for power
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conf/dac/RabaeySBBFHNSY03
Design for manufacturability and global routing
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Design analysis techniques
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conf/dac/DamaseviciusMS03
Embedded hardware design case studies
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Emerging design and tool challenges in RF and wireless applications
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Uri Barkai :
Seamless multi-radio integration challenges.
72
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COT-customer owned trouble
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conf/dac/DahlbergRBGKPRSV03 export record as
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Low-power embedded system design
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Dexin Li ,
Qiang Xie ,
Pai H. Chou :
Scalable modeling and optimization of mode transitions based on decoupled power management architecture.
119-124
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Cyclic and non-cyclic combinational circuit synthesis
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Managing leakage power
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conf/dac/MukhopadhyayRR03 export record as
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Dongwoo Lee ,
David Blaauw :
Static leakage reduction through simultaneous threshold voltage and state assignment.
191-194
Emerging markets:
design goes global
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Model order reduction
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Emad Gad ,
Michel S. Nakhla :
Model order reduction of nonuniform transmission lines using integrated congruence transform.
238-243
Issues in partitioning & design space epolartion for codesign
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Nano technology:
design implications and CAD challenges
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Gary H. Bernstein :
Quantum-dot cellular automata: computing by field polarization.
268-273
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Mixed signals on mixed-signal:
the right next technology
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conf/dac/RutenbarHJKMRS03
Simulation coverage and generation for verification
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Alon Gluska :
Coverage-oriented verification of banias.
280-285
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Shai Fine ,
Avi Ziv :
Coverage directed test generation for functional verification using bayesian networks.
286-291
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Tool support for architectural decisions in embedded systems
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New topics in logic synthesis
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Arash Saifhashemi ,
Hossein Pedram :
Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction.
330-333
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Coping with variability:
the end of deterministic design
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Fast, cheap and under control:
the next implementation fabric
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conf/dac/El-GamalBBHMOP03
Testbench, verification and debugging:
practical considerations
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Delay and noise modeling in the nanometer regime
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John F. Croix ,
D. F. Wong :
Blade and razor: cell and interconnect delay analysis using current-based models.
386-389
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Modeling issues in the design of embedded systems
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How application/technology evolutions will shape classical EDA?
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Greg Spirakis :
Leading-edge and future design challenges - is the classical EDA ready?
416
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Akira Matsuzawa :
How to make efficient communication, collaboration, and optimization from system to chip.
417-418
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SAT and BDD algorithms for verification tools
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Elements of functional and performance analysis
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Marek Jersak ,
Rolf Ernst :
Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals.
454-459
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Nonlinear model order reduction
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Novel techniques in high-level synthesis
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Mixed-signal design and simulation
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Payam Heydari :
Characterizing the effects of clock jitter due to substrate noise in discrete-time D/S modulators.
532-537
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Vinita Vasudevan ,
M. Ramakrishna :
Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique.
538-541
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Nanometer design:
place your bets
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Novel self-test methods
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Technology mapping, buffering, and bus design
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Compilation techniques for reconfigurable devices
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Architectural power estimation and optimization
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Libraries:
Lifejacket or straitjacket
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Techniques for reconfigurable logic applications
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Test and diagnosis for complex designs
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Highlights of ISSCC:
high-speed heterogeneous design techniques
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conf/dac/BorgattiCSFILMPPR03
Highlights of ISSCC and the design of state-of-the-art microprocessors
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conf/dac/AndoYISAMMMOYSKYS03 Hisashige Ando ,
Yuuji Yoshida ,
Aiichiro Inoue ,
Itsumi Sugiyama ,
Takeo Asakawa ,
Kuniki Morita ,
Toshiyuki Muta ,
Tsuyoshi Motokurumada ,
Seishi Okada ,
Hideo Yamashita ,
Yoshihiko Satsukawa ,
Akihiko Konmoto ,
Ryouichi Yamashita ,
Hiroyuki Sugiyama :
A 1.3GHz fifth generation SPARC64 microprocessor.
702-705
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Formal verification - prove it or pitch it
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High frequency interconnect modeling
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Hao Yu ,
Lei He :
Vector potential equivalent circuit based on PEEC inversion.
718-723
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conf/dac/GorenZGWBALSTGPJSSDH03 David Goren ,
Michael Zelikson ,
Rachel Gordin ,
Israel A. Wagner ,
Anastasia Barger ,
Alon Amir ,
Betty Livshitz ,
Anatoly Sherman ,
Youri Tretiakov ,
Robert A. Groves ,
J. Park ,
Donald L. Jordan ,
Sue E. Strang ,
Raminderpal Singh ,
Carl E. Dickey ,
David L. Harame :
On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices.
724-727
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Novel approaches in test coast reduction
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Retargetable tools for embedded software
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Wei Qin ,
Sharad Malik :
Automated synthesis of efficient binary decoders for retargetable software toolkits.
764-769
ASIC design in nanometer era - dead or alive?
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conf/dac/BittlestoneHSA03 export record as
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conf/dac/PileggiSSGKKPRT03 export record as
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Floorplanning and placement
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Advances in SAT
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Novel design methodologies and signal integrity
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Kaijian Shi ,
Graig Godwin :
Hybrid hierarchical timing closure methodology for a high performance and low power DSP.
850-855
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Imad A. Ferzli ,
Farid N. Najm :
Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations.
856-859
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Memory optimization for embedded systems
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Tony Givargis :
Improved indexing for cache miss reduction in embedded systems.
875-880
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Yoonseo Choi ,
Taewhan Kim :
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design.
881-886
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Design automation for quantum circuits
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Ben Travaglione :
Designing and implementing small quantum circuits and algorithms.
894-899
Energy-aware system design
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Peng Rong ,
Massoud Pedram :
Extending the lifetime of a network of battery-powered mobile devices by remote processing: a markovian decision-based approach.
906-911
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Budgeting, simulation and statistical timing
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conf/dac/BozorgzadehGTS03 export record as
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Interconnect noise avoidance methodologies & slew rate prediction
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Rajesh Kumar :
Interconnect and noise immunity design for the Pentium 4 processor.
938-943
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Analog design space exploration
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