40. DAC 2003: Anaheim, CA, USA

Real challenges and solutions for validating system-on-chip

Reshaping EDA for power

Design for manufacturability and global routing

Design analysis techniques

Embedded hardware design case studies

Emerging design and tool challenges in RF and wireless applications

COT-customer owned trouble

Low-power embedded system design

Cyclic and non-cyclic combinational circuit synthesis

Managing leakage power

Emerging markets: design goes global

Model order reduction

Issues in partitioning & design space epolartion for codesign

Nano technology: design implications and CAD challenges

Mixed signals on mixed-signal: the right next technology

Simulation coverage and generation for verification

Tool support for architectural decisions in embedded systems

New topics in logic synthesis

Coping with variability: the end of deterministic design

Fast, cheap and under control: the next implementation fabric

Testbench, verification and debugging: practical considerations

Delay and noise modeling in the nanometer regime

Modeling issues in the design of embedded systems

How application/technology evolutions will shape classical EDA?

SAT and BDD algorithms for verification tools

Elements of functional and performance analysis

Nonlinear model order reduction

Novel techniques in high-level synthesis

Mixed-signal design and simulation

Nanometer design: place your bets

Novel self-test methods

Technology mapping, buffering, and bus design

Compilation techniques for reconfigurable devices

Architectural power estimation and optimization

Libraries: Lifejacket or straitjacket

Techniques for reconfigurable logic applications

Test and diagnosis for complex designs

Highlights of ISSCC: high-speed heterogeneous design techniques

Highlights of ISSCC and the design of state-of-the-art microprocessors