Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003.
ACM 2003, ISBN 1-58113-688-9
40. DAC 2003:
Anaheim, CA, USA
Real challenges and solutions for validating system-on-chip
: High level formal verification of next-generation microprocessors.
: Improvements in functional simulation addressing challenges in large, distributed industry projects.
Reshaping EDA for power
Design for manufacturability and global routing
Design analysis techniques
Embedded hardware design case studies
Emerging design and tool challenges in RF and wireless applications
: Seamless multi-radio integration challenges.
COT-customer owned trouble
Low-power embedded system design
, Qiang Xie
, Pai H. Chou
: Scalable modeling and optimization of mode transitions based on decoupled power management architecture.
Cyclic and non-cyclic combinational circuit synthesis
Managing leakage power
, David Blaauw
: Static leakage reduction through simultaneous threshold voltage and state assignment.
design goes global
Model order reduction
Issues in partitioning & design space epolartion for codesign
design implications and CAD challenges
Mixed signals on mixed-signal:
the right next technology
Simulation coverage and generation for verification
: Coverage-oriented verification of banias.
, Avi Ziv
: Coverage directed test generation for functional verification using bayesian networks.
Tool support for architectural decisions in embedded systems
New topics in logic synthesis
Coping with variability:
the end of deterministic design
Fast, cheap and under control:
the next implementation fabric
Testbench, verification and debugging:
Delay and noise modeling in the nanometer regime
Modeling issues in the design of embedded systems
How application/technology evolutions will shape classical EDA?
: Leading-edge and future design challenges - is the classical EDA ready?
: How to make efficient communication, collaboration, and optimization from system to chip.
SAT and BDD algorithms for verification tools
Elements of functional and performance analysis
Nonlinear model order reduction
Novel techniques in high-level synthesis
Mixed-signal design and simulation
: Characterizing the effects of clock jitter due to substrate noise in discrete-time D/S modulators.
, M. Ramakrishna
: Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique.
place your bets
Novel self-test methods
Technology mapping, buffering, and bus design
Compilation techniques for reconfigurable devices
Architectural power estimation and optimization
Lifejacket or straitjacket
Techniques for reconfigurable logic applications
Test and diagnosis for complex designs
Highlights of ISSCC:
high-speed heterogeneous design techniques
Highlights of ISSCC and the design of state-of-the-art microprocessors
, Yuuji Yoshida
, Aiichiro Inoue
, Itsumi Sugiyama
, Takeo Asakawa
, Kuniki Morita
, Toshiyuki Muta
, Tsuyoshi Motokurumada
, Seishi Okada
, Hideo Yamashita
, Yoshihiko Satsukawa
, Akihiko Konmoto
, Ryouichi Yamashita
, Hiroyuki Sugiyama
: A 1.3GHz fifth generation SPARC64 microprocessor.
Formal verification - prove it or pitch it
High frequency interconnect modeling
, Lei He
: Vector potential equivalent circuit based on PEEC inversion.
, Michael Zelikson
, Rachel Gordin
, Israel A. Wagner
, Anastasia Barger
, Alon Amir
, Betty Livshitz
, Anatoly Sherman
, Youri Tretiakov
, Robert A. Groves
, J. Park
, Donald L. Jordan
, Sue E. Strang
, Raminderpal Singh
, Carl E. Dickey
, David L. Harame
: On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices.
Novel approaches in test coast reduction
Retargetable tools for embedded software
, Sharad Malik
: Automated synthesis of efficient binary decoders for retargetable software toolkits.
ASIC design in nanometer era - dead or alive?
Floorplanning and placement
Advances in SAT
Novel design methodologies and signal integrity
, Graig Godwin
: Hybrid hierarchical timing closure methodology for a high performance and low power DSP.
Imad A. Ferzli
, Farid N. Najm
: Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations.
Memory optimization for embedded systems
Design automation for quantum circuits
: Designing and implementing small quantum circuits and algorithms.
Energy-aware system design
Budgeting, simulation and statistical timing
Interconnect noise avoidance methodologies & slew rate prediction
Analog design space exploration