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ORCIDEdward J. McCluskey
Edward Joseph McCluskey Jr.
Person information
- affiliation: Stanford University, USA
- award (2012): IEEE John von Neumann Medal
- award (2008): Computer Pioneer Award
- award (1996): IEEE Emanuel R. Piore Award
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2010 – 2019
- 2016
[j73]Paolo Montuschi
, Edward J. McCluskey, Samarjit Chakraborty, Jason Cong, Ramón M. Rodríguez-Dagnino, Fred Douglis, Lieven Eeckhout, Gernot Heiser, Sushil Jajodia, Ruby B. Lee, Dinesh Manocha, Tomás F. Pena, Isabelle Puaut, Hanan Samet, Donatella Sciuto:
State of the Journal. IEEE Trans. Computers 65(7): 2014-2018 (2016)- 2010
- [j72]Ahmad A. Al-Yamani, Edward J. McCluskey:
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns. J. Electron. Test. 26(5): 513-521 (2010)
2000 – 2009
- 2008
- [c142]Jaekwang Lee, Edward J. McCluskey:
Failing Frequency Signature Analysis. ITC 2008: 1-8 - [c141]Intaik Park, Edward J. McCluskey:
Launch-on-Shift-Capture Transition Tests. ITC 2008: 1-9 - [c140]François-Fabien Ferhani, Nirmal R. Saxena, Edward J. McCluskey, Phil Nigh:
How Many Test Patterns are Useless? VTS 2008: 23-28 - [c139]Intaik Park, Donghwi Lee, Erik Chmelar, Edward J. McCluskey:
Inconsistent Fail due to Limited Tester Timing Accuracy. VTS 2008: 47-52 - [c138]Jaekwang Lee, Intaik Park, Edward J. McCluskey:
Error Sequence Analysis. VTS 2008: 255-260 - 2007
- [c137]Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey:
California scan architecture for high quality and low power testing. ITC 2007: 1-10 - [c136]Kyoung Youn Cho, Edward J. McCluskey:
Test Set Reordering Using the Gate Exhaustive Test Metric. VTS 2007: 199-204 - 2006
- [c135]François-Fabien Ferhani, Edward J. McCluskey:
Classifying Bad Chips and Ordering Test Sets. ITC 2006: 1-10 - [c134]Erik Chmelar, Edward J. McCluskey:
Session Abstract. VTS 2006: 156-157 - 2005
- [j71]Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey:
Optimized reseeding by seed ordering and encoding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2): 264-270 (2005) - [j70]Chien-Mo James Li, Edward J. McCluskey:
Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1748-1759 (2005) - [j69]Ahmad A. Al-Yamani, Edward J. McCluskey:
Test chip experimental results on high-level structural test. ACM Trans. Design Autom. Electr. Syst. 10(4): 690-701 (2005) - [c133]Ahmad A. Al-Yamani, Edward J. McCluskey:
BIST-Guided ATPG. ISQED 2005: 244-249 - [c132]Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey:
Gate exhaustive testing. ITC 2005: 7 - [c131]Intaik Park, Ahmad A. Al-Yamani, Edward J. McCluskey:
Effective TARO Pattern Generation. VTS 2005: 161-166 - 2004
- [j68]Subhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey:
Reconfigurable Architecture for Autonomous Self-Repair. IEEE Des. Test Comput. 21(3): 228-240 (2004) - [j67]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
Efficient Design Diversity Estimation for Combinational Circuits. IEEE Trans. Computers 53(11): 1483-1492 (2004) - [c130]Ahmad A. Al-Yamani, Edward J. McCluskey:
Test quality for high level structural test. HLDVT 2004: 109-114 - [c129]Kenneth A. Brand, Erik H. Volkerink, Edward J. McCluskey, Subhasish Mitra:
Speed Clustering of Integrated Circuits. ITC 2004: 1128-1137 - [c128]Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, François-Fabien Ferhani, Edward Li, Subhasish Mitra:
ELF-Murphy Data on Defects and Test Sets. VTS 2004: 16-22 - [c127]Subhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger:
Delay Defect Screening using Process Monitor Structures. VTS 2004: 43-52 - [c126]Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure:
A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. VTS 2004: 154-170 - 2003
- [c125]Ahmad A. Al-Yamani, Edward J. McCluskey:
Seed encoding with LFSRs and cellular automata. DAC 2003: 560-565 - [c124]Ahmad A. Al-Yamani, Edward J. McCluskey:
Built-In Reseeding for Serial Bist. VTS 2003: 63-68 - [c123]Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey:
Bist Reseeding with very few Seeds. VTS 2003: 69-76 - 2002
- [j66]Nahmsuk Oh, Subhasish Mitra, Edward J. McCluskey:
ED4I: Error Detection by Diverse Data and Duplicated Instructions. IEEE Trans. Computers 51(2): 180-199 (2002) - [j65]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
A Design Diversity Metric and Analysis of Redundant Systems. IEEE Trans. Computers 51(5): 498-510 (2002) - [j64]Nahmsuk Oh, Philip P. Shirvani, Edward J. McCluskey:
Error detection by duplicated instructions in super-scalar processors. IEEE Trans. Reliab. 51(1): 63-75 (2002) - [j63]Nahmsuk Oh, Philip P. Shirvani, Edward J. McCluskey:
Control-flow checking by software signatures. IEEE Trans. Reliab. 51(1): 111-122 (2002) - [j62]Nahmsuk Oh, Edward J. McCluskey:
Error detection by selective procedure call duplication for low energy consumption. IEEE Trans. Reliab. 51(4): 392-402 (2002) - [c122]Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey:
Testing Digital Circuits with Constraints. DFT 2002: 195-206 - [c121]Subhasish Mitra, Edward J. McCluskey:
Dependable Reconfigurable Computing Design Diversity and Self Repair. Evolvable Hardware 2002: 5 - [c120]Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey:
Fault Grading FPGA Interconnect Test Configurations. ITC 2002: 608-617 - [c119]Chao-Wen Tseng, James Li, Edward J. McCluskey:
Experimental Results for Slow-Speed Testing. VTS 2002: 37-42 - [c118]Chien-Mo James Li, Edward J. McCluskey:
Diagnosis of Sequence-Dependent Chips. VTS 2002: 187-192 - [c117]Subhasish Mitra, Edward J. McCluskey, Samy Makar:
Design for Testability and Testing of IEEE 1149.1 Tap Controller. VTS 2002: 247-252 - [c116]Edward J. McCluskey, Subhasish Mitra, Bob Madge, Peter C. Maxwell, Phil Nigh, Mike Rodgers:
Debating the Future of Burn-In. VTS 2002: 311-314 - 2001
- [j61]Nur A. Touba, Edward J. McCluskey:
Bit-fixing in pseudorandom sequences for scan BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(4): 545-555 (2001) - [c115]Shu-Yi Yu, Edward J. McCluskey:
Permanent Fault Repair for FPGAs with Limited Redundant Area. DFT 2001: 125-133 - [c114]Nahmsuk Oh, Edward J. McCluskey:
Procedure Call Duplication: Minimization of Energy Consumption with Constrained Error Detection Latency. DFT 2001: 182- - [c113]Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey:
Fast Run-Time Fault Location in Dependable FPGA-Based Applications. DFT 2001: 206-214 - [c112]Ahmad A. Al-Yamani, Nahmsuk Oh, Edward J. McCluskey:
Performance Evaluation of Checksum-Based ABFT. DFT 2001: 461- - [c111]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
Techniques for Estimation of Design Diversity for Combinational Logic Circuits. DSN 2001: 25-36 - [c110]Wei-Je Huang, Edward J. McCluskey:
Column-Based Precompiled Configuration Techniques for FPGA. FCCM 2001: 137-146 - [c109]Wei-Je Huang, Edward J. McCluskey:
A memory coherence technique for online transient error recovery of FPGA configurations. FPGA 2001: 183-192 - [c108]Subhasish Mitra, Edward J. McCluskey:
Diversity Techniques for Concurrent Error Detection. ISQED 2001: 249-250 - [c107]Shu-Yi Yu, Edward J. McCluskey:
On-line testing and recovery in TMR systems for real-time applications. ITC 2001: 240-249 - [c106]Chao-Wen Tseng, Edward J. McCluskey:
Multiple-output propagation transition fault test. ITC 2001: 358-366 - [c105]Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey:
Testing for resistive opens and stuck opens. ITC 2001: 1049-1058 - [c104]Chien-Mo James Li, Edward J. McCluskey:
Diagnosis of Tunneling Opens. VTS 2001: 22-27 - [c103]Subhasish Mitra, Edward J. McCluskey:
Design Diversity for Concurrent Error Detection in Sequential Logic Circuts. VTS 2001: 178-183 - [c102]Subhasish Mitra, Edward J. McCluskey:
Design of Redundant Systems Protected Against Common-Mode Failures. VTS 2001: 190-197 - [c101]Chao-Wen Tseng, Ray Chen, Edward J. McCluskey, Phil Nigh:
MINVDD Testing for Weak CMOS ICs. VTS 2001: 339-345 - [c100]Chao-Wen Tseng, Subhasish Mitra, Edward J. McCluskey, Scott Davidson:
An Evaluation of Pseudo Random Testing for Detecting Real Defects. VTS 2001: 404-410 - 2000
- [j60]Nirmal R. Saxena, Santiago Fernández-Gomez, Wei-Je Huang, Subhasish Mitra, Shu-Yi Yu, Edward J. McCluskey:
Dependable Computing and Online Testing in Adaptive and Configurable Systems. IEEE Des. Test Comput. 17(1): 29-41 (2000) - [j59]Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey:
Efficient Multiplexer Synthesis Techniques. IEEE Des. Test Comput. 17(4): 90-97 (2000) - [j58]Philip P. Shirvani, Nirmal R. Saxena, Edward J. McCluskey:
Software-implemented EDAC protection against SEUs. IEEE Trans. Reliab. 49(3): 273-284 (2000) - [j57]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
Common-mode failures in redundant VLSI systems: a survey. IEEE Trans. Reliab. 49(3): 285-295 (2000) - [c99]Shu-Yi Yu, Nirmal R. Saxena, Edward J. McCluskey:
An ACS Robotic Control Algorithm with Fault Tolerant Capabilities. FCCM 2000: 175-184 - [c98]Wei-Je Huang, Nirmal R. Saxena, Edward J. McCluskey:
A Reliable LZ Data Compressor on Reconfigurable Coprocessors. FCCM 2000: 249-258 - [c97]Chien-Mo James Li, Edward J. McCluskey:
Testing for tunneling opens. ITC 2000: 85-94 - [c96]Subhasish Mitra, Edward J. McCluskey:
Combinational logic synthesis for diversity in duplex systems. ITC 2000: 179-188 - [c95]Edward J. McCluskey, Chao-Wen Tseng:
Stuck-fault tests vs. actual defects. ITC 2000: 336-343 - [c94]Subhasish Mitra, Edward J. McCluskey:
Which concurrent error detection scheme to choose ? ITC 2000: 985-994 - [c93]Wei-Je Huang, Edward J. McCluskey:
Transient errors and rollback recovery in LZ compression. PRDC 2000: 128-138 - [c92]Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao, David M. Wu:
Cold Delay Defect Screening. VTS 2000: 183-188 - [c91]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
Fault Escapes in Duplex Systems. VTS 2000: 453-458 - [c90]Subhasish Mitra, Edward J. McCluskey:
Word Voter: A New Voter Design for Triple Modular Redundant Systems. VTS 2000: 465-470
1990 – 1999
- 1999
- [j56]Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey:
An output encoding problem and a solution technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6): 761-768 (1999) - [j55]Nur A. Touba, Edward J. McCluskey:
RP-SYN: synthesis of random pattern testable circuits with test point insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8): 1202-1213 (1999) - [c89]Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey:
A design diversity metric and reliability analysis for redundant systems. ITC 1999: 662-671 - [c88]Chaohuang Zeng, Nirmal R. Saxena, Edward J. McCluskey:
Finite state machine synthesis with concurrent error detection. ITC 1999: 672-679 - [c87]Philip P. Shirvani, Edward J. McCluskey:
PADded Cache: A New Fault-Tolerance Technique for Cache Memories. VTS 1999: 440-445 - 1998
- [c86]Jonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey:
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip. ITC 1998: 184-193 - [c85]Jonathan T.-Y. Chang, Edward J. McCluskey:
Detecting resistive shorts for CMOS domino circuits. ITC 1998: 890-899 - [c84]Nirmal R. Saxena, Edward J. McCluskey:
Dependable adaptive computing systems-the ROAR project. SMC 1998: 2172-2177 - [c83]Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu, Sanjay Wattal, Mike Purtell, Edward J. McCluskey:
Experimental Results for IDDQ and VLV Testing. VTS 1998: 118-125 - 1997
- [j54]Nirmal R. Saxena, Edward J. McCluskey:
Parallel Signatur Analysis Design with Bounds on Aliasing. IEEE Trans. Computers 46(4): 425-438 (1997) - [j53]Nur A. Touba, Edward J. McCluskey:
Logic synthesis of multilevel circuits with concurrent error detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 783-789 (1997) - [c82]Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey:
An output encoding problem and a solution technique. ICCAD 1997: 304-307 - [c81]Nur A. Touba, Edward J. McCluskey:
Pseudo-Random Pattern Testing of Bridging Faults. ICCD 1997: 54-60 - [c80]Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey:
Scan Synthesis for One-Hot Signals. ITC 1997: 714-722 - [c79]Samy Makar, Edward J. McCluskey:
ATPG for scan chain latches and flip-flops. VTS 1997: 364-369 - [c78]Robert B. Norwood, Edward J. McCluskey:
High-Level Synthesis for Orthogonal Sca. VTS 1997: 370-375 - [c77]Jonathan T.-Y. Chang, Edward J. McCluskey:
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs. VTS 1997: 446- - 1996
- [j52]Nirmal R. Saxena, Edward J. McCluskey:
Counting Two-State Transition-Tour Sequences. IEEE Trans. Computers 45(11): 1337-1342 (1996) - [c76]Nur A. Touba, Edward J. McCluskey:
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST. ITC 1996: 167-175 - [c75]Jonathan T.-Y. Chang, Edward J. McCluskey:
Detecting Delay Flaws by Very-Low-Voltage Testing. ITC 1996: 367-376 - [c74]Robert B. Norwood, Edward J. McCluskey:
Orthogonal Scan: Low-Overhead Scan for Data Paths. ITC 1996: 659-668 - [c73]Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin Chu, Sanjay Wattal, Edward J. McCluskey, Robert L. Stokes, William D. Farwell:
Analysis and Detection of Timing Failures in an Experimental Test Chip. ITC 1996: 691-700 - [c72]Nur A. Touba, Edward J. McCluskey:
Test point insertion based on path tracing. VTS 1996: 2-8 - [c71]Robert B. Norwood, Edward J. McCluskey:
Synthesis-for-scan and scan chain ordering. VTS 1996: 87-92 - [c70]Jonathan T.-Y. Chang, Edward J. McCluskey:
Quantitative analysis of very-low-voltage testing. VTS 1996: 332-337 - [c69]Nur A. Touba, Edward J. McCluskey:
Applying two-pattern tests using scan-mapping. VTS 1996: 393-399 - 1995
- [j51]Kiyoshi Furuya, Seiji Seki, Edward J. McCluskey:
Design of Autonomous TPG Circuits for Use in Two-Pattern Testing. IEICE Trans. Inf. Syst. 78-D(7): 882-888 (1995) - [j50]Daniel Boley, Gene H. Golub, Samy Makar, Nirmal R. Saxena, Edward J. McCluskey:
Floating Point Fault Tolerance with Backward Error Assertions. IEEE Trans. Computers 44(2): 302-311 (1995) - [j49]Siyad C. Ma, Edward J. McCluskey:
Open faults in BiCMOS gates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5): 567-575 (1995) - [c68]Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey:
A simple technique for locating gate-level faults in combinational circuits. Asian Test Symposium 1995: 65-70 - [c67]Samy Makar, Edward J. McCluskey:
Functional Tests for Scan Chain Latches. ITC 1995: 606-615 - [c66]Piero Franco, William D. Farwell, Robert L. Stokes, Edward J. McCluskey:
An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design. ITC 1995: 653-662 - [c65]Siyad C. Ma, Piero Franco, Edward J. McCluskey:
An Experimental Chip to Evaluate Test Techniques: Experiment Results. ITC 1995: 663-672 - [c64]Nur A. Touba, Edward J. McCluskey:
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST. ITC 1995: 674-682 - [c63]Shridhar K. Mukund, Edward J. McCluskey, T. R. N. Rao:
An apparatus for pseudo-deterministic testing. VTS 1995: 125-131 - [c62]Samy Makar, Edward J. McCluskey:
Checking experiments to test latches. VTS 1995: 196-201 - [c61]Nur A. Touba, Edward J. McCluskey:
Transformed pseudo-random patterns for BIST. VTS 1995: 410-416 - 1994
- [j48]Nirmal R. Saxena, Edward J. McCluskey:
Linear Complexity Assertions for Sorting. IEEE Trans. Software Eng. 20(6): 424-431 (1994) - [c60]Nur A. Touba, Edward J. McCluskey:
Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. ICCAD 1994: 651-654 - [c59]Nur A. Touba, Edward J. McCluskey:
Automated Logic Synthesis of Random-Pattern-Testable Circuits. ITC 1994: 174-183 - [c58]Piero Franco, Edward J. McCluskey:
On-line delay testing of digital circuits. VTS 1994: 167-173 - [c57]Siyad C. Ma, Edward J. McCluskey:
Open faults in BiCMOS gates. VTS 1994: 434-439 - [c56]Piero Franco, Edward J. McCluskey:
Three-pattern tests for delay faults. VTS 1994: 452-456 - 1993
- [j47]Hong Hao, Edward J. McCluskey:
Analysis of Gate Oxide Shorts in CMOS Circuits. IEEE Trans. Computers 42(12): 1510-1516 (1993) - [c55]Hong Hao, Edward J. McCluskey:
Very-Low-Voltage Testing for Weak CMOS Logic ICs. ITC 1993: 275-284 - [c54]Edward J. McCluskey:
Quality and Single-Stuck Faults. ITC 1993: 597 - [c53]LaNae J. Avra, Edward J. McCluskey:
Synthesizing for Scan Dependence in Built-In Self-Testable Desings. ITC 1993: 734-743 - 1992
- [j46]Nirmal R. Saxena, Piero Franco, Edward J. McCluskey:
Simple Bounds on Serial Signature Analysis Aliasing for Random Testing. IEEE Trans. Computers 41(5): 638-645 (1992) - [c52]Siyad C. Ma, Edward J. McCluskey:
Non-Conventional Faults in BiCMOS Digital Circuits. ITC 1992: 882-891 - 1991
- [c51]