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Jihong Ren
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2020 – today
- 2024
- [j8]Yonggang Ji, Xinling Wang, Farui Li, Jihong Ren, Taoli Li, Yiming Wang, Weifeng Sun:
Ambiguity Elimination of Vessel Target Azimuth for Shipborne HFSWR. IEEE Trans. Aerosp. Electron. Syst. 60(4): 4429-4440 (2024) - 2023
- [j7]Yonggang Ji, Xiaoyu Cheng, Yiming Wang, Weifeng Sun, Xi Zhang, Meicheng Jiang, Jihong Ren, Farui Li:
Motion Compensation Method Using Direct Wave Signal for CTSR Bistatic HFSWR. IEEE Geosci. Remote. Sens. Lett. 20: 1-5 (2023)
2010 – 2019
- 2015
- [j6]Reza Navid, E-Hung Chen, Masum Hossain, Brian S. Leibowitz, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble:
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology. IEEE J. Solid State Circuits 50(4): 814-827 (2015) - 2014
- [c13]E-Hung Chen, Masum Hossain, Brian S. Leibowitz, Reza Navid, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble:
A 40-Gb/s serial link transceiver in 28-nm CMOS technology. VLSIC 2014: 1-2 - [c12]Masum Hossain, E-Hung Chen, Reza Navid, Brian S. Leibowitz, Chuen-Huei Adam Chou, Simon Li, Myeong-Jae Park, Jihong Ren, Barry Daly, Bruce Su, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble:
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering. VLSIC 2014: 1-2 - 2012
- [c11]Kambiz Kaviani, Masum Hossain, Meisam Honarvar Nazari, Fred Heaton, Jihong Ren, Jared Zerbe:
A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS. CICC 2012: 1-4 - 2011
- [j5]Jared Zerbe, Barry Daly, Lei Luo, Bill Stonecypher, Wayne D. Dettloff, John C. Eble, Teva Stone, Jihong Ren, Brian S. Leibowitz, Michael Bucher, Patrick Satarzadeh, Qi Lin, Yue Lu, Ravi T. Kollipara:
A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques. IEEE J. Solid State Circuits 46(4): 974-985 (2011) - [j4]Jaeha Kim, E-Hung Chen, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Jared Zerbe, Chih-Kong Ken Yang:
Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2096-2107 (2011) - 2010
- [c10]Jaeha Kim, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Ali-Azam Abbasfar, Jared Zerbe:
Equalizer design and performance trade-offs in ADC-based serial links. CICC 2010: 1-8
2000 – 2009
- 2009
- [j3]Jaeha Kim, Brian S. Leibowitz, Jihong Ren, Chris J. Madden:
Simulation and Analysis of Random Decision Errors in Clocked Comparators. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1844-1857 (2009) - [c9]Jaeha Kim, Jihong Ren, Mark A. Horowitz:
Stochastic steady-state and AC analyses of mixed-signal systems. DAC 2009: 376-381 - 2008
- [j2]E-Hung Chen, Jihong Ren, Brian S. Leibowitz, Hae-Chang Lee, Qi Lin, Kyung Suk Oh, Frank Lambrecht, Vladimir Stojanovic, Jared Zerbe, Chih-Kong Ken Yang:
Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric. IEEE J. Solid State Circuits 43(9): 2144-2156 (2008) - [c8]Brian S. Leibowitz, Jaeha Kim, Jihong Ren, Chris J. Madden:
Characterization of random decision errors in clocked comparators. CICC 2008: 691-694 - 2007
- [j1]Jihong Ren, Chen Greif, Mark R. Greenstreet:
An efficient linear programming solver for optimal filter synthesis. Numer. Linear Algebra Appl. 14(9): 695-712 (2007) - [c7]Suwen Yang, Mark R. Greenstreet, Jihong Ren:
A Jitter Attenuating Timing Chain. ASYNC 2007: 25-38 - 2006
- [c6]Mark R. Greenstreet, Jihong Ren:
Surfing Interconnect. ASYNC 2006: 98-106 - 2005
- [c5]Jihong Ren, Mark R. Greenstreet:
A unified optimization framework for equalization filter synthesis. DAC 2005: 638-643 - 2004
- [c4]Jihong Ren, Mark R. Greenstreet:
A Signal Integrity Test Bed for PCB Buses. ICCD 2004: 132-137 - [c3]Jihong Ren, Mark R. Greenstreet:
Crosstalk Cancellation for Realistic PCB Buses. PATMOS 2004: 48-57 - 2003
- [c2]Jihong Ren, Mark R. Greenstreet:
Synthesizing optimal filters for crosstalk-cancellation for high-speed buses. DAC 2003: 592-597 - [c1]Jihong Ren, Mark R. Greenstreet:
Equalizing Filter Design for Crosstalk Cancellation. ISVLSI 2003: 272-274
Coauthor Index
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last updated on 2024-09-10 02:05 CEST by the dblp team
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