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"A simple technique for locating gate-level faults in combinational circuits."

Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey (1995)

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DOI: 10.1109/ATS.1995.485318

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
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  - https://dblp.org/rec/conf/ats/YamadaYM95
Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey:
A simple technique for locating gate-level faults in combinational circuits. Asian Test Symposium 1995: 65-70

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