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ORCID15th ISCA 1988: Honolulu, Hawaii, USA
- Howard Jay Siegel:
Proceedings of the 15th Annual International Symposium on Computer Architecture, Honolulu, Hawaii, USA, May-June 1988. IEEE Computer Society 1988, ISBN 0-8186-0861-7 - Joydeep Ghosh, Kai Hwang:
Critical Issues in Mapping Neural Networks on Message-Passing Multicomputers. 3-11 - Yoshiyasu Takefuji
, Robert J. Jannarone, Yong B. Cho, Tatung Chen:
Multinomial Conjunctoid Statistical Learning Machines. 12-17 - Ahmed Louri, Kai Hwang:
A Bit-Plane Architecture for Optical Computing with Two-Dimensional Symbolic Substitution. 18-27 - Stuart Fiske, William J. Dally:
The Reconfigurable Arithmetic Processor. 30-36 - Andrew R. Pleszkun, Gurindar S. Sohi:
The Performance Potential of Multiple Functional Unit Processors. 37-44 - Wen-mei W. Hwu, Pohua P. Chang:
Exploiting Parallel Microprocessor Microarchitectures With a Compiler Code Generator. 45-53 - Geoffrey D. McNiven, Edward S. Davidson:
Analysis of Memory Referencing Behavior For Design of Local Memories. 56-63 - Richard J. Eickemeyer, Janak H. Patel:
Performance Evaluation of On-Chip Register and Cache Organizations. 64-72 - Jean-Loup Baer, Wen-Hann Wang:
On the Inclusion Properties for Multi-Level Cache Hierarchies. 73-80 - Robert T. Short, Henry M. Levy:
A Simulation Study of Two-Level Caches. 81-88 - E. T. Chow, H. Madan, John C. Peterson, Dirk Grunwald, Daniel A. Reed:
Hyperswitch Network for the Hypercube Computer. 90-99 - Donald C. Winsor, Trevor N. Mudge:
Analysis of Bus Hierarchies for Multiprocessors. 100-107 - Sizheng Wei, Gyungho Lee:
Extra Group Network: A Cost-Effective Fault-Tolerant Multistage Interconnection Network. 108-115 - Hong Jiang, Kenneth C. Smith:
A Partial-Multiple-Bus Computer Structure with Improved Cost-Effectiveness. 116-122 - Ian Watson, Viv Woods, Paul Watson, Richard Banach, Mark Irvine Greenberg, John Sargeant:
Flagship: A Parallel Architecture for Declarative Programming. 124-130 - Robert A. Iannucci:
Toward a Dataflow/von Neumann Hybrid Architecture. 131-140 - David E. Culler, Arvind:
Resource Requirements of Dataflow Programs. 141-150 - Brinkley Sprunt, David Blair Kirk, Lui Sha:
Priority-Driven, Preemptive I/O Controllers for Real-Time Systems. 152-159 - Shridhar B. Shukla, Dharma P. Agrawal:
A Kernel-independent, Pipelined Architecture for Real-Time 2-D Convolution. 160-166 - Wentai Liu, Tong-Fei Yeh, William E. Batchelor, Ralph K. Cavin III:
Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions. 167-174 - Douglas W. Clark, Peter J. Bannon, James B. Keller:
Measuring VAX 8800 Performance with a Histogram Hardware Monitor. 176-185 - Richard L. Sites, Anant Agarwal:
Multiprocessor Cache Analysis Using ATUM. 186-195 - Spencer W. Ng, Dorothy Lang, Robert Selinger:
Trade-offs Between Devices and Paths in Achieving Disk Interleaving. 196-201 - Kishan Jainandunsing, Ed F. Deprettere:
Design of a Concurrent Computer for Solving Systems of Linear Equations. 204-211 - Andrew Wolfe, Maurício Breternitz Jr., Chriss Stephens, A. L. Ting, David Blair Kirk, Ronald P. Bianchini Jr., John Paul Shen:
The White Dwarf: A High-Performance Application-Specific Processor. 212-222 - Jean-Luc Gaudiot, C. M. Lin, M. Hosseiniyar:
Solving Partial Differential Equations in a Data-Driven Multiprocessor Environment. 223-230 - De-Lei Lee:
Scrambled Storage for Parallel Memory Systems. 232-239 - Venkatesh Krishnaswamy, Sudhir Ahuja, Nicholas Carriero, David Gelernter:
The Architecture of a Linda Coprocessor. 240-249 - H. T. Kung:
Deadlock Avoidance for Systolic Communication. 252-260 - Kimming So, Vittorio Zecca:
Cache Performance of Vector Processors. 261-268 - Mary K. Vernon, Udi Manber:
Distributed Round-Robin and First-Come First-Serve Protocols and Their Application to Multiprocessor Bus Arbitration. 269-277 - Anant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz:
An Evaluation of Directory Schemes for Cache Coherence. 280-289 - Steven A. Przybylski, Mark Horowitz, John L. Hennessy:
Performance Tradeoffs in Cache Design. 290-298 - Hoichi Cheong, Alexander V. Veidenbaum:
A Cache Coherence Scheme With Fast Selective Invalidation. 299-307 - Mary K. Vernon, Edward D. Lazowska, John Zahorjan:
An Accurate and Efficient Performance Analysis Technique for Multiprocessor Snooping Cache-Consistency Protocols. 308-315 - Darwen Rau, José A. B. Fortes, Howard Jay Siegel:
Destination Tag Routing Techniques Based on a State Model for the IADM Network. 318-324 - Doug W. Kim, G. Jack Lipovski, Alfred C. Hartmann, Roy M. Jenevein:
Regular CC-Banyan Networks. 325-332 - Roy M. Jenevein, Thomas Mookken:
Traffic Analysis of Rectangular SW-Banyan Networks. 333-342 - Yuval Tamir, Gregory L. Frazier:
High-Performance Multi-Queue Buffers for VLSI Communication Switches. 343-354 - Bruno R. Preiss, V. Carl Hamacher:
A Cache-based Message Passing Scheme for a Shared-bus Multiprocessor. 358-364 - Taisuke Boku, Shigehiro Nomura, Hideharu Amano:
IMPULSE: A High Performance Processing Unit for Multiprocessors for Scientific Calculation. 365-372 - Susan J. Eggers, Randy H. Katz:
A Characterization of Sharing in Parallel Programs and Its Application to Coherency Protocol Evaluation. 373-382 - G. Jack Lipovski, Paul Vaughan:
A Fetch-And-Op Implementation for Parallel Computers. 384-392 - André Seznec, Yvon Jégou:
Synchronizing Processors Through Memory Requests in a Tightly Coupled Multiprocessor. 393-400 - Richard Fujimoto, Jya-Jang Tsai, Ganesh Gopalakrishnan:
Design and Performance of Special Purpose Hardware for Time Warp. 401-408 - David R. Cheriton, Anoop Gupta, Patrick D. Boyle, Hendrik A. Goosen:
The VMP Multiprocessor: Initial Experience, Refinements and Performance Evlauation. 410-421 - James R. Goodman, Philip J. Woest:
The Wisconsin Multicube: A New Large-Scale Cache-Coherent Multiprocessor. 422-431 - Evan Tick:
Data Buffer Performance for Sequential Prolog Architectures. 434-442 - Robert H. Halstead Jr., Tetsuya Fujita:
MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing. 443-451 - Philip L. Butler, J. D. Allen Jr., Donald W. Bouldin:
Parallel Architecture for OPS5. 452-457
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