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ORCIDBo Yao 0004
Person information
- affiliation: Mentor Graphics Corporation, Wilsonville, OR, USA
- affiliation: University of California, San Diego, Department of Computer Science and Engineering, CA, USA
Other persons with the same name
- Bo Yao — disambiguation page
- Bo Yao 0001 — University of Essex, Computational Intelligence Centre, School of Computer Science and Electronic Engineering, Colchester, UK
- Bo Yao 0002 — Intel Corp., Hillsboro, OR, USA (and 1 more)
- Bo Yao 0003
![[0000-0003-1852-2774]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-1852-2774")
— Lancaster University, Department of Psychology, Fylde College, UK (and 2 more) - Bo Yao 0005 — Chinese Academy of Medical Sciences, Peking Union Medical College, Institute of Biomedical Engineering, Tianjin, China
- Bo Yao 0006 — Xidian University, School of Aerospace Science and Technology, Key Laboratory of Equipment Efficiency in Extreme Environment, Xi'an, China
- Bo Yao 0007 — Fudan University, School of Computer Science, Shanghai, China
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2010 – 2019
- 2011
[j4]Ling Zhang, Yulei Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng:
On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 520-524 (2011)
2000 – 2009
- 2007
- [j3]Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng:
Efficient Timing Analysis With Known False Paths Using Biclique Covering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 959-969 (2007) - [c14]Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng:
Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. ISQED 2007: 251-256 - 2006
- [c13]Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton:
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. ASP-DAC 2006: 73-78 - 2005
- [j2]Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao:
The Y architecture for on-chip interconnect: analysis and methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 588-599 (2005) - [c12]Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng:
Integrated algorithmic logical and physical design of integer multiplier. ASP-DAC 2005: 1014-1017 - [c11]Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris:
Improving the efficiency of static timing analysis with false paths. ICCAD 2005: 527-531 - [c10]Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris:
Unified quadratic programming approach for mixed mode placement. ISPD 2005: 193-199 - 2004
- [c9]Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng:
A multiple level network approach for clock skew minimization with process variations. ASP-DAC 2004: 263-268 - [r1]Zhou Feng, Bo Yao, Chung-Kuan Cheng:
Floorplan Representation in VLSI. Handbook of Data Structures and Applications 2004 - 2003
- [j1]Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham:
Floorplan representations: Complexity and connections. ACM Trans. Design Autom. Electr. Syst. 8(1): 55-80 (2003) - [c8]Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng:
The Y-architecture: yet another on-chip interconnect solution. ASP-DAC 2003: 840-847 - [c7]Zhengyong Zhu, Bo Yao, Chung-Kuan Cheng:
Power network analysis using an adaptive algebraic multigrid approach. DAC 2003: 105-108 - [c6]Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu:
An algebraic multigrid solver for analytical placement with layout based clustering. DAC 2003: 794-799 - [c5]Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao:
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. ICCAD 2003: 13-20 - [c4]Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham:
A hierarchical three-way interconnect architecture for hexagonal processors. SLIP 2003: 133-139 - 2002
- [c3]Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng:
Physical Planning Of On-Chip Interconnect Architectures. ICCD 2002: 30-35 - [c2]Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham:
Balancing the Interconnect Topology for Arrays of Processors between Cost and Power. ICCD 2002: 180-186 - 2001
- [c1]Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham:
Revisiting floorplan representations. ISPD 2001: 138-143
Coauthor Index
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