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ORCIDYuichiro Miyaoka
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2000 – 2009
- 2006
[c8]Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. ASP-DAC 2006: 594-599- 2005
- [j4]Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 876-884 (2005) - [j3]Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. IEICE Trans. Inf. Syst. 88-D(7): 1340-1349 (2005) - [c7]Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A processor core synthesis system in IP-based SoC design. ASP-DAC 2005: 286-291 - [c6]Nozomu Togawa
, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. ISCAS (4) 2005: 3499-3502 - 2004
- [c5]Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A cosynthesis algorithm for application specific processors with heterogeneous datapaths. ASP-DAC 2004: 250-255 - [c4]Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
Instruction set and functional unit synthesis for SIMD processor cores. ASP-DAC 2004: 743-750 - 2003
- [j2]Nozomu Togawa, Kyosuke Kasahara, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki:
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3099-3109 (2003) - [j1]Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3218-3224 (2003) - [c3]Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki:
A hardware/software partitioning algorithm for SIMD processor cores. ASP-DAC 2003: 135-140 - 2002
- [c2]Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. APCCAS (1) 2002: 171-176 - 2001
- [c1]Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Area/delay estimation for digital signal processor cores. ASP-DAC 2001: 156-161
Coauthor Index
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