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ORCIDKazutoshi Wakabayashi
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2020 – today
- 2024
[c32]Kento Mishima, Naoya Niwa
, Kazutoshi Wakabayashi, Hiroe Iwasaki:
ISP Parameter Optimization and FPGA Implementation for Object Detection in Low-Light Conditions. COOL CHIPS 2024: 1-3- 2021
- [c31]Hiroaki Suzuki, Wataru Takahashi, Kazutoshi Wakabayashi, Hideharu Amano:
A programming environment for multi-FPGA systems based on CyberWorkBench: an integrated design tool. HEART 2021: 5:1-5:6 - 2020
- [c30]Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi:
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC 2020: 502-504
2010 – 2019
- 2019
- [c29]Toki Matsumoto, Yukikazu Nakamoto, Ryota Yamamoto, Shinya Honda, Kazutoshi Wakabayashi:
Convolution Neural Network Development Support System using Approximation Methods to Evaluate Inference Accuracy and Memory Usage in an Embedded System. SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI 2019: 1312-1317 - 2018
- [j21]Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto:
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. 10(4): 119-122 (2018) - [j20]Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto:
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2723-2736 (2018) - 2016
- [j19]Takashi Kishimoto, Wataru Takahashi, Kazutoshi Wakabayashi, Hiroyuki Ochi:
Range Limiter Using Connection Bounding Box for SA-Based Placement of Mixed-Grained Reconfigurable Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2328-2334 (2016) - [c28]Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto:
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL 2016: 1-4 - 2015
- [c27]Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera:
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC 2015: 14-15 - 2014
- [j18]Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera:
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2518-2529 (2014) - [c26]Kazutoshi Wakabayashi, Takashi Takenaka, Hiroaki Inoue:
Mapping complex algorithm into FPGA with High Level Synthesis reconfigurable chips with High Level Synthesis compared with CPU, GPGPU. ASP-DAC 2014: 282-284 - 2013
- [c25]Kazutoshi Wakabayashi:
Reconfigurable chip advantage compared with GPGPU from the compiler perspective. FPT 2013: 2 - [c24]Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye:
Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design. ReConFig 2013: 1-6 - 2012
- [j17]Benjamin Carrión Schäfer, Kazutoshi Wakabayashi:
Machine learning predictive modelling high-level synthesis design space exploration. IET Comput. Digit. Tech. 6(3): 153-159 (2012) - [j16]Benjamin Carrión Schäfer, Kazutoshi Wakabayashi:
Divide and conquer high-level synthesis design space exploration. ACM Trans. Design Autom. Electr. Syst. 17(3): 29:1-29:19 (2012) - 2011
- [j15]Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano:
Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2619-2627 (2011) - [j14]Benjamin Carrión Schäfer, Kazutoshi Wakabayashi:
Precision tunable RTL macro-modelling cycle-accurate power estimation. IET Comput. Digit. Tech. 5(2): 95-103 (2011) - 2010
- [j13]Wolfgang Rosenstiel, Kazutoshi Wakabayashi:
CODES+ISSS 2009 guest editors' introduction. Des. Autom. Embed. Syst. 14(3): 229-230 (2010) - [j12]Benjamin Carrión Schäfer, Yusuke Iguchi, Wataru Takahashi, Shingo Nagatani, Kazutoshi Wakabayashi:
Fixed Point Data Type Modeling for High Level Synthesis. IEICE Trans. Electron. 93-C(3): 361-368 (2010) - [j11]Kazutoshi Wakabayashi:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2371 (2010) - [j10]Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi:
High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor. Inf. Media Technol. 5(2): 398-411 (2010) - [j9]Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi:
High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor. IPSJ Trans. Syst. LSI Des. Methodol. 3: 91-104 (2010) - [j8]Benjamin Carrión Schäfer, Kazutoshi Wakabayashi:
Design Space Exploration Acceleration Through Operation Clustering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(1): 153-157 (2010) - [c23]Benjamin Carrión Schäfer, Ashish Trambadia, Kazutoshi Wakabayashi:
Design of complex image processing systems in ESL. ASP-DAC 2010: 809-814 - [c22]Kazutoshi Wakabayashi:
Real-time multimedia with C compiler for Hardware. ESTIMedia 2010 - [c21]Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano:
Wire congestion aware synthesis for a dynamically reconfigurable processor. FPT 2010: 300-303 - [c20]Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum:
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems. ISLPED 2010: 49-54
2000 – 2009
- 2009
- [e2]Kazutoshi Wakabayashi:
Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009. IEEE 2009, ISBN 978-1-4244-2748-2 [contents] - [e1]Wolfgang Rosenstiel, Kazutoshi Wakabayashi:
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009. ACM 2009, ISBN 978-1-60558-628-1 [contents] - 2008
- [j7]Reinaldo A. Bergamaschi, Luca Benini, Krisztián Flautner, Wido Kruijtzer, Alberto L. Sangiovanni-Vincentelli, Kazutoshi Wakabayashi:
The State of ESL Design [Roundtable]. IEEE Des. Test Comput. 25(6): 510-519 (2008) - 2007
- [j6]Liangwei Ge, Song Chen, Kazutoshi Wakabayashi, Takashi Takenaka, Takeshi Yoshimura:
Max-Flow Scheduling in High-Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(9): 1940-1948 (2007) - [c19]Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayashi:
Synthesizing "Verification Aware" Models: Why and How? VLSI Design 2007: 50-56 - 2006
- [j5]Kazutoshi Wakabayashi:
Unified Representation for Speculative Scheduling: Generalized Condition Vector. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3408-3415 (2006) - [c18]Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing:
High-level synthesis challenges and solutions for a dynamically reconfigurable processor. ICCAD 2006: 702-708 - 2005
- [c17]Jason Cong, Tony Ma, Ivo Bolsens, Phil Moorby, Jan M. Rabaey, John Sanguinetti, Kazutoshi Wakabayashi, Yoshi Watanabe:
Are we ready for system-level synthesis? ASP-DAC 2005 - [c16]Kazutoshi Wakabayashi:
System LSI design with C-based behavioral synthesis and verification. ISCAS (6) 2005: 5930-5933 - 2004
- [c15]Kazutoshi Wakabayashi:
C-based behavioral synthesis and verification analysis on industrial design examples. ASP-DAC 2004: 344-348 - [c14]Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima:
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. FCCM 2004: 328-329 - [c13]Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima:
Stream applications on the dynamically reconfigurable processor. FPT 2004: 137-144 - 2003
- [j4]Hidefumi Kurokawa, Hiroyuki Ikegami, Motohide Otsubo, Kiyoshi Asao, Kazuhisa Kirigaya, Katsuya Misu, Satoshi Takahashi, Tetsuji Kawatsu, Kouji Nitta, Hiroshi Ryu, Kazutoshi Wakabayashi, Minoru Tomobe, Wataru Takahashi, Akira Mukouyama, Takashi Takenaka:
Study and Analysis of System LSI Design Methodologies Using C-Based Behavioral Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(4): 787-798 (2003) - 2002
- [j3]Kazutoshi Wakabayashi:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 733 (2002) - [c12]Aarti Gupta, Albert E. Casavant, Pranav Ashar, Sean Liu, Akira Mukaiyama, Kazutoshi Wakabayashi:
Property-Specific Testbench Generation for Guided Simulation. ASP-DAC/VLSI Design 2002: 524- - 2001
- [c11]Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar:
Property-specific witness graph generation for guided simulation. DATE 2001: 799 - 2000
- [j2]Kazutoshi Wakabayashi, Takumi Okamoto:
C-based SoC design flow and EDA tools: an ASIC and system vendorperspective. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(12): 1507-1522 (2000) - [c10]Koichiro Furuta, Taro Fujii, Masato Motomura, Kazutoshi Wakabayashi, Masakazu Yamashina:
Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI. CICC 2000: 151-154
1990 – 1999
- 1999
- [j1]Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi:
Controller-based power management for control-flow intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10): 1496-1508 (1999) - [c9]Kazutoshi Wakabayashi:
C-based Synthesis Experiences with a Behavior Synthesizer, "Cyber". DATE 1999: 390- - 1997
- [c8]Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi:
Power Management Techniques for Control-Flow Intensive Designs. DAC 1997: 429-434 - 1996
- [c7]Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi:
Controller re-specification to minimize switching activity in controller/data path circuits. ISLPED 1996: 301-304 - 1995
- [c6]Masayuki Yuguchi, Yuichi Nakamura, Kazutoshi Wakabayashi, Tomoyuki Fujita:
Multi-Level Logic Minimization Based on Multi-Signal Implications. DAC 1995: 658-662 - [c5]Jan M. Rabaey, Miodrag Potkonjak, Kazutoshi Wakabayashi:
Efficient throughput optimization of feedback linear computations using generalized Horner's scheme. ICASSP 1995: 2659-2662 - [c4]Miodrag Potkonjak, Sujit Dey, Kazutoshi Wakabayashi:
Design-for-debugging of application specific designs. ICCAD 1995: 295-301 - 1992
- [c3]Kazutoshi Wakabayashi, Hirohito Tanaka:
Global Scheduling Independent of Control Dependencies Based on Condition Vectors. DAC 1992: 112-115
1980 – 1989
- 1989
- [c2]Kazutoshi Wakabayashi, Takeshi Yoshimura:
A resource sharing and control synthesis method for conditional branches. ICCAD 1989: 62-65 - 1985
- [c1]Gotaro Odawara, Kazuhiko Iijima, Kazutoshi Wakabayashi:
Knowledge-based placement technique for printed wiring boards. DAC 1985: 616-622
Coauthor Index
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