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2020 – today
- 2023
[j81]Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera:
Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 542-550 (2023)- 2022
- [j80]Yih-Lang Li
, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera:
NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5568-5581 (2022) - [c138]Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera:
Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region. LASCAS 2022: 1-4 - [c137]Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera:
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits. SOCC 2022: 1-6 - 2021
- [j79]Hongjie Xu, Jun Shiomi, Hidetoshi Onodera:
Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1488-1498 (2021) - [j78]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1546-1554 (2021) - [j77]Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera:
Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1566-1576 (2021) - [j76]Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera:
A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation. IEICE Trans. Electron. 104-C(10): 617-624 (2021) - [j75]Shinichi Nishizawa, Shih-Ting Lin, Yih-Lang Li, Hidetoshi Onodera:
Supplemental PDK for ASAP7 Using Synopsys Flow. IPSJ Trans. Syst. LSI Des. Methodol. 14: 24-26 (2021) - [j74]Hongjie Xu, Jun Shiomi, Hidetoshi Onodera:
MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching. IEEE Open J. Circuits Syst. 2: 144-155 (2021) - [c136]Jun Shiomi, Shuya Kotsugi, Boyu Dong, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics. DAC 2021: 139-144 - [c135]Kensuke Murakami, Mahfuzul Islam, Hidetoshi Onodera:
CDF Distance Based Statistical Parameter Extraction Using Nonlinear Delay Variation Models. IOLTS 2021: 1-6 - 2020
- [j73]Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera:
Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. IEICE Trans. Electron. 103-C(10): 489-496 (2020) - [c134]Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera:
A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias. APCCAS 2020: 31-34 - [c133]Hongjie Xu, Jun Shiomi, Hidetoshi Onodera:
On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation. ACM Great Lakes Symposium on VLSI 2020: 21-26 - [c132]Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hidetoshi Onodera:
MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing. ICCAD 2020: 157:1-157:8 - [c131]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. ICRC 2020: 95-101 - [c130]Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi:
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC 2020: 502-504 - [c129]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. ISVLSI 2020: 488-493 - [c128]Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera:
Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region. SoCC 2020: 236-241
2010 – 2019
- 2019
- [j72]Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
A Design Method of a Cell-Based Amplifier for Body Bias Generation. IEICE Trans. Electron. 102-C(7): 565-572 (2019) - [j71]Akira Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, Keiji Kishine, Hidetoshi Onodera:
Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity. IEICE Trans. Electron. 102-C(7): 573-579 (2019) - [j70]Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1741-1750 (2019) - [j69]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1751-1759 (2019) - [j68]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing. Integr. 65: 201-210 (2019) - [j67]A. K. M. Mahfuzul Islam, Hidetoshi Onodera:
Circuit Techniques for Device-Circuit Interaction toward Minimum Energy Operation. IPSJ Trans. Syst. LSI Des. Methodol. 12: 2-12 (2019) - [c127]Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing. ASP-DAC 2019: 203-209 - [c126]Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera:
NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map. DAC 2019: 120 - [c125]A. K. M. Mahfuzul Islam, Ryota Shimizu, Hidetoshi Onodera:
Analysis of Random Telegraph Noise (RTN) at Near-Threshold Operation by Measuring 154k Ring Oscillators. IRPS 2019: 1-6 - [c124]Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera:
A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. SoCC 2019: 150-154 - 2018
- [j66]Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto:
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. 10(4): 119-122 (2018) - [j65]Shinichi Nishizawa, Hidetoshi Onodera:
Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2222-2230 (2018) - [j64]Jun Shiomi, Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera:
Minimum Energy Point Tracking with All-Digital On-Chip Sensors. J. Low Power Electron. 14(2): 227-235 (2018) - [j63]Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto:
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2723-2736 (2018) - [c123]Akitaka Hiratsuka, Akira Tsuchiya, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera:
A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation. A-SSCC 2018: 69-72 - [c122]A. K. M. Mahfuzul Islam, Hidetoshi Onodera:
PVT2: process, voltage, temperature and time-dependent variability in scaled CMOS process. ICCAD 2018: 126 - [c121]Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi:
Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics. ICRC 2018: 1-8 - [c120]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing. ICRC 2018: 1-6 - [c119]Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera:
Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation. IOLTS 2018: 177-182 - [c118]Shinichi Nishizawa, Hidetoshi Onodera:
Process variation aware D-Flip-Flop design using regression analysis. ISQED 2018: 88-93 - [c117]Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology. MWSCAS 2018: 751-754 - [c116]A. K. M. Mahfuzul Islam, Hidetoshi Onodera:
Worst-Case Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage Variability. PATMOS 2018: 140-146 - [c115]Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure. PATMOS 2018: 237-242 - [c114]Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera:
Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization. SoCC 2018: 112-117 - 2017
- [j62]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2764-2775 (2017) - [j61]Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera:
A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2776-2784 (2017) - [c113]Akitaka Hiratsuka, Akira Tsuchiya, Hidetoshi Onodera:
Power-bandwidth trade-off analysis of multi-stage inverter-type transimpedance amplifier for optical communication. MWSCAS 2017: 795-798 - [c112]Islam A. K. M. Mahfuzul, Hidetoshi Onodera:
Effect of supply voltage on random telegraph noise of transistors under switching condition. PATMOS 2017: 1-8 - [c111]Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera:
Pin accessibility evaluating model for improving routability of VLSI designs. SoCC 2017: 56-61 - [c110]Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera:
On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator. VLSI-DAT 2017: 1-4 - 2016
- [j60]Hidetoshi Onodera:
2016 ASP-DAC. IEEE Des. Test 33(3): 133-134 (2016) - [j59]Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Analytical Stability Modeling for CMOS Latches in Low Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2463-2472 (2016) - [c109]Islam A. K. M. Mahfuzul, Hidetoshi Onodera:
On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations. ASP-DAC 2016: 403-409 - [c108]Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. ASP-DAC 2016: 691-696 - [c107]Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto:
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL 2016: 1-4 - [c106]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Variability- and correlation-aware logical effort for near-threshold circuit design. ISQED 2016: 18-23 - [c105]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing. PATMOS 2016: 44-49 - [c104]Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera:
Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing. SoCC 2016: 1-6 - 2015
- [j58]Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera:
Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets. IEICE Trans. Electron. 98-C(4): 298-303 (2015) - [j57]Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera:
A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage. IEICE Trans. Electron. 98-C(6): 504-511 (2015) - [j56]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1455-1466 (2015) - [j55]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell. IPSJ Trans. Syst. LSI Des. Methodol. 8: 131-135 (2015) - [j54]Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring. IEEE J. Solid State Circuits 50(11): 2475-2490 (2015) - [j53]Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera:
A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1288-1295 (2015) - [c103]Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera:
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC 2015: 14-15 - [c102]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Microarchitectural-level statistical timing models for near-threshold circuit design. ASP-DAC 2015: 87-93 - [c101]Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura:
A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking. A-SSCC 2015: 1-4 - [c100]Chenjie Gu, Hidetoshi Onodera:
Session 23 - Modeling emerging devices. CICC 2015: 1 - [c99]Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
An energy-efficient on-chip memory structure for variability-aware near-threshold operation. ISQED 2015: 23-28 - [c98]Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera:
Energy reduction by built-in body biasing with single supply voltage operation. ISQED 2015: 181-185 - [c97]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
An impact of process variation on supply voltage dependence of logic path delay variation. VLSI-DAT 2015: 1-4 - 2014
- [j52]Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera:
A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(3): 734-740 (2014) - [j51]SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera:
Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(3): 768-776 (2014) - [j50]SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera:
Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure. IEICE Trans. Electron. 97-C(4): 325-331 (2014) - [j49]Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera:
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2518-2529 (2014) - [j48]Bishnu Prasad Das, Hidetoshi Onodera:
On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator. IEEE Trans. Circuits Syst. II Express Briefs 61-II(3): 183-187 (2014) - [j47]Bishnu Prasad Das, Hidetoshi Onodera:
Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2535-2548 (2014) - [c96]Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring. A-SSCC 2014: 45-48 - [c95]Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Hidetoshi Onodera:
A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation. A-SSCC 2014: 53-56 - [c94]Yukio Mitsuyama, Hidetoshi Onodera:
Variability and Soft-Error Resilience in Dependable VLSI Platform. ATS 2014: 45-50 - [c93]Takashi Matsumoto, Kazutoshi Kobayashi, Hidetoshi Onodera:
Impact of random telegraph noise on CMOS logic circuit reliability. CICC 2014: 1-8 - [c92]Colin McAndrew, Hidetoshi Onodera:
Modeling of advanced devices. CICC 2014: 1 - [c91]Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai:
A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops. ISCAS 2014: 2704-2707 - [c90]Tomohiro Fujita, SinNyoung Kim, Hidetoshi Onodera:
Computer simulation of radiation-induced clock-perturbation in phase-locked loop with analog behavioral model. ISQED 2014: 230-235 - [c89]Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Variation-aware Flip-Flop energy optimization for ultra low voltage operation. SoCC 2014: 17-22 - [c88]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. SoCC 2014: 42-47 - [c87]Islam A. K. M. Mahfuzul, Hidetoshi Onodera:
Characterization and compensation of performance variability using on-chip monitors. VLSI-DAT 2014: 1-4 - 2013
- [j46]Kuiyuan Zhang, Jun Furuta, Ryosuke Yamamoto, Kazutoshi Kobayashi, Hidetoshi Onodera:
A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect. IEICE Trans. Electron. 96-C(4): 511-517 (2013) - [j45]Islam A. K. M. Mahfuzul, Hidetoshi Onodera:
On-Chip Detection of Process Shift and Process Spread for Post-Silicon Diagnosis and Model-Hardware Correlation. IEICE Trans. Inf. Syst. 96-D(9): 1971-1979 (2013) - [j44]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2499-2507 (2013) - [c86]Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS. ASP-DAC 2013: 105-106 - [c85]Hidetoshi Onodera:
Dependable VLSI Platform using Robust Fabrics. ASP-DAC 2013: 119-124 - [c84]Hidetoshi Onodera, Yu Kevin Cao:
AMS verification in advanced technologies. CICC 2013: 1 - [c83]SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera:
Perturbation-immune radiation-hardened PLL with a switchable DMR structure. IOLTS 2013: 128-132 - [c82]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Analysis and comparison of XOR cell structures for low voltage circuit design. ISQED 2013: 703-708 - 2012
- [j43]Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 479-486 (2012) - [j42]Bishnu Prasad Das, Hidetoshi Onodera:
Area-efficient reconfigurable-array-based oscillator for standard cell characterisation. IET Circuits Devices Syst. 6(6): 429-436 (2012) - [c81]Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS. ASP-DAC 2012: 561-562 - [c80]Islam A. K. M. Mahfuzul, Hidetoshi Onodera:
On-Chip Detection of Process Shift and Process Spread for Silicon Debugging and Model-Hardware Correlation. Asian Test Symposium 2012: 350-354 - [c79]Trent McConaghy, Hidetoshi Onodera:
Modeling & design for variability and reliability. CICC 2012: 1-2 - [c78]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
A flexible structure of standard cell and its optimization method for near-threshold voltage operation. ICCD 2012: 235-240 - [c77]Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
A Standard Cell Optimization Method for Near-Threshold Voltage Operations. PATMOS 2012: 32-41 - 2011
- [j41]Chikara Hamanaka, Ryosuke Yamamoto, Jun Furuta, Kanto Kubota, Kazutoshi Kobayashi, Hidetoshi Onodera:
Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2669-2675 (2011) - [j40]Hidetoshi Onodera:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 4: 1 (2011) - [c76]Jun Furuta, Chikara Hamanaka, Kazutoshi Kobayashi, Hidetoshi Onodera:
A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. ASP-DAC 2011: 83-84 - [c75]Jun Furuta, Ryosuke Yamamoto, Kazutoshi Kobayashi, Hidetoshi Onodera:
Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm. A-SSCC 2011: 209-212 - [c74]Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera:
An area effective forward/reverse body bias generator for within-die variability compensation. A-SSCC 2011: 217-220 - [c73]Hidetoshi Onodera:
Dependable VLSI Program in Japan: Program Overview and the Current Status of Dependable VLSI Platform Project. Asian Test Symposium 2011: 492-495 - [c72]Akira Tsuchiya, Takeshi Kuboki, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi Onodera:
Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors. ISOCC 2011: 36-39 - [c71]