Cover

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  International Test Conference - Cover.
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  International Test Conference - Title Page.
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  International Test Conference - Copyright.

Introduction

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  Welcoming Message.
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  Steering Committee and Subcommittees.
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  Ned Kornfield Memorial.
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  2003 Paper Awards.
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  Technical Program Committee.
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  ITC Technical Paper Evaluation and Selection Process.
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  2005 Call for Papers.
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  TTTC: Test Technology Technical Council.
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  Technical Paper Reviewers.

Session 1: Plenary

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  Bernd Koenemann: Test In the Era of "What You see Is NOT What You Get". 12
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  Robert Madge: New Test Paradigms for Yield and Manufacturability. 13

Session 2: Microprocessor Test

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  Benoit Provost, Chee How Lim, Mo Bashir, Ali Muhtaroglu, Tiffany Huang, Kathy Tian, Mubeen Atha, Cangsang Zhao, Harry Muljono: AC IO Loopback Design for High Speed µProcessor IO Test. 23-30
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  Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham: On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. 31-37
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  David M. Wu, Mike Lin, Madhukar Reddy, Talal Jaber, Anil Sabbavarapu, Larry Thatcher: An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor. 38-47

Session 3: Logic BIST

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  Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers: Efficient Pattern Mapping for Deterministic Logic BIST. 48-56
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  Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng: Logic BIST with Scan Chain Segmentation. 57-66
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  Omar I. Khan, Michael L. Bushnell: Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing. 67-76

Session 4: BIST for Jitter

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  Takahiro J. Yamaguchi, Masahiro Ishida, Kiyotaka Ichiyama, Mani Soma, Christian Krawinkel, Katsuaki Ohsawa, Masao Sugai: A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems. 77-84
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  Karen Taylor, Bryan Nelson, Alan Chong, Hieu Nguyen, Henry C. Lin, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz: Experimental Results for High-Speed Jitter Measurement Technique. 85-94
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  Stephen K. Sunter, Aubin Roy, Jean-Francois Cote: An Automated, Complete, Structural Test Solution for SERDES. 95-104

Session 5: Memory Testing

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  Benjamin M. Mauck, Vishnumohan Ravichandran, Usman Azeez Mughal: A Design for Test Technique for Parametric Analysis of SRAM: On-Die Low Yield Analysis. 105-113
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  A. J. van de Goor, Said Hamdioui, Rob Wadsworth: Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests. 114-123
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  Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu: MRAM Defect Analysis and Fault Modeli. 124-133

Session 6: Failure Characterization Methods for IC Diagnosis

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  Stas Polonsky, Keith A. Jenkins, Alan J. Weger, Shinho Cho: CMOS IC diagnostics using the luminescence of OFF-state leakage currents. 134-139
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  Peilin Song, Franco Stellari, Alan J. Weger, Tian Xia: A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current. 140-147
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  Vijay Reddy, John Carulli, Anand T. Krishnan, William Bosch, Brendan Burgess: Impact of Negative Bias Temperature Instability on Product Parametric Drift. 148-155

Session 7: Board and System Test: At-Speed and Bounce-Free

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  Heon C. Kim, Hong Shin Jun, Xinli Gu, Sung Soo Chung: At-Speed Interconnect Test and Diagnosis of External Memories on a System. 156-162
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  Kendrick Baker, Mehrdad Nourani: Interconnect Test Pattern Generation Algorithm For Meeting Device and Global SSO Limits With Safe Initial Vectors. 163-172
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  Hong Shin Jun, Sung Soo Chung, Sang H. Baeg: Removing JTAG Bottlenecks in System Interconnect Test. 173-180

Session 8: Methods and Strategies for Optimal Test

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  Manu Rehani, David Abercrombie, Robert Madge, Jim Teisher, Jason Saw: ATE Data Collection - A comprehensive requirements proposal to maximize ROI of test. 181-189
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  Jonathan Hops, Brian Swing, Brian Phelps, Bruce Sudweeks, John Pane, James Kinslow: Non-Deterministic DUT Behavior During Functional Testing of High Speed Serial Busses: Challenges and Solutions. 190-196
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  Peter Patten: Divide and Conquer based Fast Shmoo algorithms. 197-202
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  Robert Madge, Brady Benware, Ritesh P. Turakhia, W. Robert Daasch, Chris Schuermyer, Jens Ruffler: In Search of the Optimum Test Set - Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost. 203-212

Session 9: In Search of Small Delay Defects

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  Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger: On Hazard-free Patterns for Fine-delay Fault Testing. 213-222
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  Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran: K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. 223-231
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  Saravanan Padmanaban, Spyros Tragoudas: A Critical Path Selection Method for Delay Testing. 232-241
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  Haihua Yan, Adit D. Singh: Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study. 242-251

Session 10: Mixed-Signal BIST and DFT

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  Ashwin Raghunathan, Ji Hwan (Paul) Chun, Jacob A. Abraham, Abhijit Chatterjee: Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters. 252-261
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  Abhishek Singh, Chintan Patel, Jim Plusquellic: On-Chip Impulse Response Generation for Analog and Mixed-Signal Testing. 262-270
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  Foster F. Dai, Charles E. Stroud, Dayu Yang, Shuying Qi: Automatic Linearity (IP3) Test with Built-in Pattern Generator and Analyzer. 271-280
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  Geert Seuren, Tom Waayers: Extending the Digital Core-based Test Methodology to Support Mixed-Signal. 281-289

Session 11: Advances in Testing for Defects

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  Bram Kruseman, Ananta K. Majhi, Camelia Hora, Stefan Eichenberger, Johan Meirlevede: Systematic Defects in Deep Sub-Micron Technologies. 290-299
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  Chris Schuermyer, Jens Ruffler, W. Robert Daasch: Minimum Testing Requirements to Screen Temperature Dependent Defects. 300-308
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  Phil Nigh, Anne E. Gattiker: Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions. 309-318
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  Chintan Patel, Abhishek Singh, Jim Plusquellic: Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement. 319-328

Session 12: Advances in DFT

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  Matthew L. King, Kewal K. Saluja: Testing Micropipelined Asynchronous Circuits. 329-338
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  Bo Yang, Kaijie Wu, Ramesh Karri: Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard. 339-344
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  C. P. Ravikumar, Graham Hetherington: A Holistic Parallel and Hierarchical Approach towards Design-For-Test. 345-354
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  Kenneth M. Butler, Jayashree Saxena, Tony Fryars, Graham Hetherington: Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques. 355-364

Session 13: Board and System Test: Board Test Effectiveness

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  Kenneth P. Parker: A New Probing Technique for High-Speed/High-Density Printed Circuit Boards. 365-374
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  Rodger Schuttert, D. C. L. Van Geest, A. Kumar: On-Chip Mixed-Signal Test Structures Re-used for Board Test. 375-383
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  Carlos Michel, Rosa D. Reinosa: Test Strategy Cost Model Innovations. 384-392
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  Amit Verma, Charles Robinson, Steve Butkovich: Production Test Effectiveness of Combined Automated Inspection and ICT Test Strategies. 393-402

Session 14: Developments in ATE Software Standards

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  Rochit Rajsuman, Masuda Noriyuki: Open Architecture Test System: System Architecture and Design. 403-412
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  Ankan K. Pramanick, Ramachandran Krishnaswamy, Mark Elston, Toshiaki Adachi, Harsanjeet Singh, Bruce R. Parnas: Test Programming Environment in a Modular, Open Architecture Test System. 413-422
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  David Dowding, Ernie Wahl, Don Organ: Extending STIL 1450 Standard for Test Program Flow. 423-431

Session 15: Handling of Unknowns

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  Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher: X-Tolerant Signature Analysis. 432-441
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  Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker: X-Masking During Logic BIST and Its Impact on Defect Coverage. 442-451
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  Vivek Chickermane, Brian Foutz, Brion L. Keller: Channel Masking Synthesis for Efficient On-Chip Test Compression. 452-461

Session 16: Emerging Technologies Fault Modeling and Tolerance

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  Jason G. Brown, R. D. (Shawn) Blanton: CAEN-BIST: Testing the NanoFabric. 462-471
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  Wenjing Rao, Alex Orailoglu, Ramesh Karri: Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems. 472-478
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  Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi: Routability and Fault Tolerance of FPGA Interconnect Architectures. 479-488

Session 17: Advances in Diagnosis

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  Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy: Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection. 489-497
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  Grzegorz Mrugalski, Chen Wang, Artur Pogiel, Jerzy Tyszer, Janusz Rajski: Fault Diagnosis in Designs with Convolutional Compactors. 498-507
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  Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, Vyacheslav Rovner, S. Tiwary: Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. 508-517

Session 18: Test Economics

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  Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane: An Economic Analysis and ROI Model for Nanometer Test. 518-524
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  Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski: Realizing High Test Quality Goals with Smart Test Resource Usage. 525-533
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  Pamela S. Gillis, Francis Woytowich, Andrew Ferko, Kevin McCauley: Low Overhead Delay Testing of ASICS. 534-542

Session 19: Board and System Test: Extending Boundary-Scan to RF and HS Serial Testing

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  Saghir A. Shaikh: IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver. 543-550
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  Juha Häkkinen, Pekka Syri, Juha-Veikko Voutilainen, Markku Moilanen: A Frequency Mixing and Sub-Sampling Based RF-Measurement Apparatus for IEEE 1149.4. 551-559
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  Jeff Rearick, Sylvia Patterson, Krista Dorner: Integrating Boundary Scan into Multi-GHz I/O Circuitry. 560-566

Session 20: Squeezing the Picoseconds

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  Masashi Shimanouchi: Timing Accuracy Enhancement by a New Calibration Scheme for Multi-Gbps ATE. 567-576
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  Ahmed Rashid Syed: Automatic Delay Calibration Method for Multi-channel CMOS Formatter. 577-586
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  A. T. Sivaram, Pascal Pierra, Shida Sheibani, Nancy Wang-Lee, Jorge E. Solorzano, Lily Tran: Active Tester Interface Unit Design For Data Collection. 587-596

Session 21: ATPG/FAULT Simulation Specialties

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  Feng Shi, Yiorgos Makris: SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits. 597-606
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  Kameshwar Chandrasekar, Michael S. Hsiao: Decision Selection and Learning for an All-Solutions ATPG Engine. 607-616
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  Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal: On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. 617-626

Session 22: Interconnect Testing and Fault Diagnosis in FPGAS

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  Dave Mark, Jenny Fan: Localizing Open Interconnect Defects using Targeted Routing in FPGA's. 627-634
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  Mehdi Baradaran Tahoori, Subhasish Mitra: Interconnect Delay Testing of Designs on Programmable Logic Devices. 635-644
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  Mehdi Baradaran Tahoori: Application-Dependent Diagnosis of FPGAs. 645-654

Session 23: Industry Case Studies in Testing

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  A. Cabbibo, J. Conder, M. Jacobs: Feed Forward Test Methodology Utilizing Device Identification. 655-660
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  Leendert M. Huisman, Maroun Kassab, Leah Pastel: Data Mining Integrated Circuit Fails with Fail Commonalities. 661-668
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  Enamul Amyeen, Srikanth Venkataraman, Ajay Ojha, Sangbong Lee: Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor. 669-678

Session 24: Lecture Series - Test Trends and Challenges

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  Sandip Kundu, T. M. Mak, Rajesh Galivanche: Trends in manufacturing test methods and their implications. 679-687
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  Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge: Trends in Testing Integrated Circuits. 688-697
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  Alfred L. Crouch: Future Trends in Test: The Adoption and Use of Low Cost Structural Testers. 698-703

Session 25: Board and System Test: System and Field Test

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  Bill Eklow, Anoosh Hosseini, Chi Khuong, Shyam Pullela, Toai Vo, Hien Chau: Simulation Based System Level Fault Insertion Using Co-verification Tools. 704-710
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  Chen-Huan Chiang, Paul J. Wheatley, Kenneth Y. Ho, Ken L. Cheung: Testing and Remote Field Update of Distributed Base Stations in a Wireless Network. 711-718
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  Yujun Zhang, Zhongcheng Li: IPV6 Conformance Testing: Theory and Practice. 719-727

Session 26: ATE for the Fastest Devices

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  Mohamed Hafed, Antonio H. Chan, Geoffrey Duerden, Bardia Pishdad, Clarence Tam, Sebastien Laberge, Gordon W. Roberts: A High-Throughput 5 GBps Timing and Jitter Test Module Featuring Localized Processing. 728-737
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  A. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson: Tester Architecture For The Source Synchronous Bus. 738-747
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  David C. Keezer, Dany Minier, F. Binette: Modular Extension of ATE to 5 Gbps. 748-757

Session 27: SoC: Mixed Signals, Size and Speed

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  Hans T. Heineken, Jitendra Khare: Test Strategies For a 40Gbps Framer SoC. 758-763
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  Bernd Laquai: A Model-based Test Approach for Testing High-Speed PLLs and Phase Regulation Circuitry in SOC Devices. 764-772
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  K. Nikila, Rubin A. Parekhji: DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device. 773-782

Session 28: RF Testing

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  Erkan Acar, Sule Ozev: Delayed-RF Based Test Development for FM Transceivers Using Signature Analysis. 783-792
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  Dana Brown, John Ferrario, Randy Wolf, Jing Li, Jayendra Bhagat: RF Testing on a Mixed Signal Tester. 793-800
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  Soumendu Bhattacharya, Abhijit Chatterjee: Use of Embedded Sensors for Built-In-Test of RF Circuits. 801-809

Session 29: State Space Exploration and Test Generation

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  Alper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra: Formal Verification of a System-on-Chip Using Computation Slicing. 810-819
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  Qingwei Wu, Michael S. Hsiao: State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation. 820-829
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  Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang: Verification on Port Connections. 830-836

Session 30: SoC Test Case Studies

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  Charles E. Stroud, John Sunwoo, Srinivas M. Garimella, Jonathan Harris: Built-In Self-Test for System-on-Chip: A Case Study. 837-846
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  Jeff Remmers, Moe Villalba, Richard Fisette: Hierarchical DFT Methodology - A Case Study. 847-856

Session 31: Board and System Test: Board and System-Level BIST Techniques

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  C. J. Clark, Mike Ricchetti: A Code-less BIST Processor for Embedded Test and in-system configuration of Boards and Systems. 857-866
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  Liviu Miclea, Szilárd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto: Towards Microagent based DBIST/DBISR. 867-874
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  David Resnick: Embedded Test for a new Memory-Card Architecture. 875-882

Session 32: Test of Digital, Analog and MEMS C

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  Fei Su, Krishnendu Chakrabarty: Concurrent Testing of Droplet-Based Microfluidic Systems for Multiplexed Biomedical Assays. 883-892
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  Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski: Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. 893-902
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  Ali Muhtaroglu, Benoit Provost, Tawfik Rahal-Arabi, Greg Taylor: I/O Self-Leakage Test. 903-906
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  Sreejit Chakravarty, Eric W. Savage, Eric N. Tran: Defect Coverage Analysis of Partitioned Testing. 907-915

Session 33: Test Compression

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  Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai: VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. 916-925
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  Armin Würtenberger, Christofer S. Tautermann, Sybille Hellebrand: Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 926-935
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  Kedarnath J. Balakrishnan, Nur A. Touba: Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion. 936-944
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  Baris Arslan, Alex Orailoglu: Test Cost Reduction Through A Reconfigurable Scan Architecture. 945-952

Session 34: Mixed-Signal Test Techniques

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  Christopher S. Taillefer, Gordon W. Roberts: Reducing Measurement Uncertainty in a DSP-Based Mixed-Signal Test Environment without Increasing Test Time. 953-962
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  Heinz Mattes, Claus Dworski, Sebastian Sattler: Controlled Sine Wave Fitting for ADC Test. 963-971
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  Hideo Okawara: Precise Pulse Width Measurement in Write Pre-compensation Test. 972-979
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  José Pineda de Gyvez, Guido Gronthoud, Cristiano Cenci, Martin Posch, Thomas Burger, Manfred Koller: Power Supply Ramping for Quasi-static Testing of PLLs. 980-987

Session 35: Embedded Memories BIST and Repair

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  Masaji Kume, Katsutoshi Uehara, Minoru Itakura, Hideo Sawamoto, Toru Kobayashi, Masatoshi Hasegawa, Hideki Hayashi: Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI. 988-996
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  Robert C. Aitken: A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories. 997-1005
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  Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez: AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. 1006-1015
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  Osamu Wada, Toshimasa Namekawa, Hiroshi Ito, Atsushi Nakayama, Shuso Fujii: Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM. 1016-1023

Session 36: Delay Testing

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  Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer: Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models. 1024-1033
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  Manan Syal, Michael S. Hsiao, Sreejit Chakravarty: Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. 1034-1043
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  Quming Zhou, Kartik Mohanram: Analysis of delay caused by bridging faults in RLC interconnects. 1044-1052
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  Puneet Gupta, Michael S. Hsiao: ALAPTF: A new Transition Faultmodel and the ATPG Algorithm. 1053-1060

Session 37: Application Series - Board and System-Level DFT and Test

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  Charles Njinda: A Hierarchical DFT Architecture for Chip, Board and System Test/Debug. 1061-1071
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  Sunil Kalidindi, Nghia Huynh, Bill Eklow, Josh Goldstein: "Real Life" System Testing of Networking Equipment. 1072-1077
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  Thomas J. Anderson: Practical Instrumentation Integration Considerations. 1078-1080

Session 38: Formalizing and Simulating ATE

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  Baolin Deng, Wolfram Glauert: Formal Description of Test Specification and ATE Architecture for Mixed-Signal Test. 1081-1090
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  Martin Zambaldi, Wolfgang Ecker: How to Bridge the Gap Between Simulationand Test. 1091-1099
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  R. Raghuraman: Simulation Requirements for Vectors in ATE Formats. 1100-1107

Session 39: Testing for Speed - New and Practical Methods

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  Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi: A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs. 1108-1117
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  Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu: Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing. 1118-1127
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  Kenneth A. Brand, Erik H. Volkerink, Edward J. McCluskey, Subhasish Mitra: Speed Clustering of Integrated Circuits. 1128-1137

Session 40: Picosecond Jitter Testing

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  Dongwoo Hong, Chee-Kian Ong, Kwang-Ting (Tim) Cheng: BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics. 1138-1147
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  Peter M. Levine, Gordon W. Roberts: A High-Resolution Flash Time-to-Digital Converter and Calibration Scheme. 1148-1157
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  Mike Li, Andy Martwick, Gerry Talbot, Jan B. Wilstrup: Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And Applications. 1158-1167

Session 41: Application Series - Wafer Probe Technology

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  William R. Mann, Frederick L. Taber, Philip W. Seitzer, Jerry J. Broz: The Leading Edge of Production Wafer Probe Test Technology. 1168-1195

Session 42: Wrappers and More

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  Qiang Xu, Nicola Nicolici: Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores. 1196-1202
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  Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty: IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. 1203-1212
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  Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee: An SOC Test Integration Platform and Its Industrial Realization. 1213-1222

Session 43: Design-for-Availability

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  Cecilia Metra, T. M. Mak, Martin Omaña: Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. 1223-1231
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  Man Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka: Architectures of Increased Availability Wireless Sensor Network Nodes. 1232-1241
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  Kaijie Wu, Ramesh Karri, Grigori Kuznetsov, Michael Gössel: Low Cost Concurrent Error Detection for the Advanced Encryption Standard. 1242-1248

Session 44: Advances in Tester Architecture

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  Burnell G. West, Michael F. Jones: Digital Synchronization for Reconfigurable ATE. 1249-1254
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  Daisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu: 34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System. 1255-1262
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  Maurizio Gavardoni, Michael Jones, Russell Poffenberger, Miguel Conde: System Monitor for Diagnostic, Calibration and System Configuration. 1263-1268

Session 45: Advances in Delay Testing

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  Bipul Chandra Paul, Cassondra Neau, Kaushik Roy: Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits. 1269-1275
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  Sebastiàn A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura, Ali Keshavarzi: Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. 1276-1284
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  Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski: Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. 1285-1294

Session 46: Application Series - Jitter in Test

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  Andy Kuo, Touraj Farahmand, Nelson Ou, André Ivanov, Sassan Tabatabaei: Jitter Models and Measurement Methods for High-Speed Serial Interconnects. 1295-1302
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  Gert Hansel, Korbinian Stieglbauer: Implementation of an Economic Jitter Compliance Test for a Multi-Gigabit Device on ATE. 1303-1312
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  Sassan Tabatabaei, Michael Lee, Freddy Ben-Zeev: Jitter Generation and Measurement for Test of Multigbps Serial IO. 1313-1321

Session 47: On-Line Testing and Fault Tolerance at Low Cost

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  Shalini Ghosh, Nur A. Touba, Sugato Basu: Reducing Power Consumption in Memory ECC Checkers. 1322-1331
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  Fulvio Corno, Matteo Sonza Reorda, Simonluca Tosato, F. Esposito: Evaluating the Effects of Transient Faults on Vehicle Dynamic Performance in Automotive Systems. 1332-1339
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  Haibo Wang, Suchitra Kulkarni, Spyros Tragoudas: On-line Testing Field Programmable Analog Array Circuits. 1340-1348

Session 48: Advances in SoC Test

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  Erik Larsson: Integrating Core Selection in the SOC Test Solution Design-Flow. 1349-1358
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  Ozgur Sinanoglu, Alex Orailoglu: Autonomous Yet Deterministic Test of SOC Cores. 1359-1368
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  Chunsheng Liu, Hamid Sharif, Érika F. Cota, Dhiraj K. Pradhan: Test Scheduling for Network-on-Chip with BIST and Precedence Constraints. 1369-1378

Session 49: ADC Testing

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  Hanjun Jiang, Beatriz Olleta, Degang Chen, Randall L. Geiger: Testing High Resolution ADCs with Low Resolution/Accuracy Deterministic Dynamic Element Matched DACs. 1379-1388
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  Hak-soo Yu, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham: Performance Characterization of Mixed-Signal Circuits Using a Ternary Signal Representation. 1389-1397
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  Zhongjun Yu, Degang Chen, Randall L. Geiger: A Computationally Efficient Method for Accurate Spectral Testing without Requiring Coherent Sampling. 1398-1407

Panel 1: Open Architecture ATE: Reality or Dream?

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  Gordon D. Robinson: Open Architecture ATE: Dream or Reality?. 1408
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  Sergio M. Perez: The Critical Need For Open ATE Architecture. 1409
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  Burnell G. West: Open Architecture ATE: Prospects and Problems. 1410

Panel 2: Security vs. Test Quality: Can we only have one at a time?

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  Erik Jan Marinissen: Security vs. Test Quality: Can We Really Only Have One at a Time? 1411
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  Hérvé Fleury: Electronic circuit comprising a secret sub-module. 1412
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  Stephen Pateras: Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having Both. 1413
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  Rohit Kapur: Security vs. Test Quality: Are they mutually exclusive?. 1414
• 
  Laurent Sourgen: Testing a secure device: High coverage with very low observability. 1415

Panel 3: Glamorous Analog Testability - We Already Test them and Ship Them... So What is the Problem?

• 
  Mohamed Hafed: Glamorous Analog Testability - We Already Test them and Ship Them - So What is the Problem? 1416

Panel 4: 100 DPM in Nanometer Technology - Is it Achievable?

• 
  Greg Aldrich: 100 DPPM in Nanometer Technology - Is it achievable? 1417
• 
  Brady Benware: Achieving Sub 100 DPPM Defect Levels on VDSM and Nanometer ASICs. 1418
• 
  Kenneth M. Butler: Sure You Can Get to 100 DPPM in Deep Submicron, But It'll Cost Ya. 1419
• 
  Phil Nigh: Achieving Quality Levels of 100dpm: It's possible - but roll up your sleeves and be prepared to do some work.. 1420
• 
  Sanjay Sengupta: Test Strategies for Nanometer Technologies. 1421
• 
  Thomas M. Storey: Testing in a high volume DSM Environment. 1422

Panel 5: What Do You Mean My Board Test Stinks?

• 
  Bill Eklow: What Do You Mean My Board Test Stinks? 1423
• 
  Jay J. Nejedlo: Functional Test Coverage Effectiveness on the Decline. 1424
• 
  Rob Jukna: To Test or To Inspect, What is the Coverage?. 1425
• 
  Kenneth P. Parker: Board Test Coverage Needs to be Standardized. 1426
• 
  Michael J. Smith: What do you mean my Board Test stinks?. 1427

Panel 6: DUDE! Where's My Data? - Cracking Open the Hermetically Sealed Tester

• 
  W. Robert Daasch, Manu Rehani: Dude! Where's my data? - Cracking Open the Hermetically Sealed Tester. 1428
• 
  Phil Nigh: Redefining ATE: "Data Collection Engines that Drive Yield Learning and Process Optimization". 1429
• 
  Robert Madge: ATE Value Add through Open Data Collection. 1430

Panel 7: Cost of Test: Taking Control

• 
  Nilanjan Mukherjee: Cost of Test - Taking Control. 1431
• 
  Mike Tripp: ITC 2004 Panel: Cost of Test - Taking Control. 1432

Panel 8: Is "Design-to-Production" The Ultimate Answer for Jitter, Noise, and BER Challenges for Multi-GB/S ICs?

• 
  Mike Li: Is "Design to Production" The Ultimate Answer For Jitter, Noise, and BER Challenges For Multi GB/s ICs?. 1433
• 
  Takahiro J. Yamaguchi: Loopback or not? 1434
• 
  John C. Johnson: Options for High-Volume Test of Multi-GB/s Ports. 1435
• 
  Mike Li: Will "Heisenberg Uncertainty Principle" Hold For Designing and Testing Multiple GB/s ICs? 1436
• 
  Jim Sproch: A Little DFT Goes a Long Way When Testing Multi-Gb/s I/O Signals. 1437

Panel 9: Diagnosis Meets Physical Failure Analysis: How Long Can We Succeed?

• 
  Yukio Okuda: Panel Synopsis - Diagnosis Meets Physical Failure Analysis: How Long Can We Succeed? 1438
• 
  Thomas Bartenstein: Panel 9 - Diagnostics vs. Failure Analysis. 1439
• 
  Edward I. Cole Jr.: Global Failure Localization: We Have To, But on What and How?. 1440
• 
  Anne E. Gattiker: Diagnosis Meets Physical Failure Analysis: How Long can we Succeed? 1441
• 
  Srikanth Venkataraman: Diagnosis meets Physical Failure Analysis: What is needed to succeed?. 1442
• 
  Kiyoshi Nikawa: How long can we succeed using the OBIRCH and its derivatives ?. 1443

Panel 10: Investment vs. Yield Relationship for Memories in SoC

• 
  Yervant Zorian: Investment vs. Yield Relationship for Memories in SOC. 1444
• 
  Jitendra Khare: Memory Yield Improvement - SoC Design Perspective. 1445
• 
  Joseph A. Reynick: Investment vs. Yield Relationship for Memories and IP in SOC. 1446
• 
  Jun Qian: Plan Ahead for Yield. 1447

ITC 2003 Best Paper

• 
  Mike Tripp, T. M. Mak, Anne Meixner: Elimination of Traditional Functional Testing of Interface Timings at Intel. 1448-1456

last updated on Wed May 22 04:51:57 2013 by the dblp team
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