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ORCIDHans T. Heineken
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2000 – 2009
- 2004
[c13]Hans T. Heineken, Jitendra Khare:
Test Strategies For a 40Gbps Framer SoC. ITC 2004: 758-763- 2000
- [c12]Charles Ouyang, Kyungsuk Ryu, Hans T. Heineken, Jitu Khare, Saghir A. Shaikh, Manuel d'Abreu:
Wire planning for performance and yield enhancement. CICC 2000: 113-116 - [c11]Jitendra Khare, Hans T. Heineken, Manuel d'Abreu:
Cost Trade-Offs in System On Chip Designs. VLSI Design 2000: 178-184 - [c10]Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken:
Manufacturability and Testability Oriented Synthesis. VLSI Design 2000: 185-191 - [c9]Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, Saghir A. Shaikh, Manuel d'Abreu:
Maximizing Wafer Productivity Through Layout Optimization. VLSI Design 2000: 192-197
1990 – 1999
- 1998
- [c8]Hans T. Heineken, Jitendra Khare, Manuel d'Abreu:
Manufacturability analysis of standard cell libraries. CICC 1998: 321-324 - [c7]Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare:
Design-Manufacturing Interface: Part I - Vision. DATE 1998: 550-556 - [c6]Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon:
Design-Manufacturing Interface: Part II - Applications. DATE 1998: 557-562 - [c5]Hans T. Heineken, Wojciech Maly:
Performance - Manufacturability Tradeoffs in IC Design. DATE 1998: 563-567 - 1997
- [c4]Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz:
CAD at the Design-Manufacturing Interface. DAC 1997: 321-326 - [c3]Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken:
Detection of Yield Trends. DFT 1997: 62-68 - 1996
- [c2]Hans T. Heineken, Wojciech Maly:
Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. ICCAD 1996: 368-373 - [c1]Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag:
Design for manufacturability in submicron domain. ICCAD 1996: 690-697
Coauthor Index
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