BibTeX record conf/itc/WatanabeSO04

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@inproceedings{DBLP:conf/itc/WatanabeSO04,
  author    = {Daisuke Watanabe and
               Masakatsu Suda and
               Toshiyuki Okayasu},
  title     = {34.1Gbps Low Jitter, Low {BER} High-Speed Parallel {CMOS} Interface
               for Interconnections in High-Speed Memory Test System},
  booktitle = {Proceedings 2004 International Test Conference {(ITC} 2004), October
               26-28, 2004, Charlotte, NC, {USA}},
  pages     = {1255--1262},
  publisher = {{IEEE} Computer Society},
  year      = {2004},
  url       = {https://doi.org/10.1109/TEST.2004.1387399},
  doi       = {10.1109/TEST.2004.1387399},
  timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl    = {https://dblp.org/rec/conf/itc/WatanabeSO04.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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