DATE 2001:
Munich, Germany
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conf/date/EconomakosOPPP01 export record as
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Robert Siegmund ,
Dietmar Müller :
SystemCSV - an extension of SystemC for mixed multi-level communication modeling and interface-based system design.
26-33
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conf/date/ZorianPTTPDSMR01 export record as
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J. Zhu :
MetaRTL: raising the abstraction level of RTL design.
71-76
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conf/date/PaschalisGKPZ01 export record as
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conf/date/BayraktarogluO01 export record as
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Jakob Axelsson :
Methods and tools for systems engineering of automotive electronic architectures.
112
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G. Hettich ,
Thomas Thurner :
Vehicle electric/electronic architecture - one of the most important challenges for OEM's.
112-113
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Sherief Reda ,
A. Salem :
Combinational equivalence checking using Boolean satisfiability and binary decision diagrams.
122-126
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conf/date/GajskiVRGBPECJ01 export record as
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conf/date/DielissenMBHSHW01 export record as
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conf/date/SilvaSAGLSTSRNSW01 Julio Leao da Silva Jr. ,
J. Shamberger ,
M. Josie Ammer ,
C. Guo ,
Suet-Fei Li ,
Rahul C. Shah ,
Tim Tuan ,
Michael Sheets ,
Jan M. Rabaey ,
Borivoje Nikolic ,
Alberto L. Sangiovanni-Vincentelli ,
Paul K. Wright :
Design methodology for PicoRadio networks.
314-325
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conf/date/BadarogluHGDMGEB01 export record as
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Lech Józwiak ,
Artur Chojnacki :
High-quality sub-function construction in functional decomposition based on information relationship measures.
383-390
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Qinwei Xu ,
Pinaki Mazumder :
Efficient and passive modeling of transmission lines by using differential quadrature method.
437-444
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Qingjian Yu ,
Ernest S. Kuh :
Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements.
445-450
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Tom Chen :
On the impact of on-chip inductance on signal nets under the influence of power grid noise.
451-459
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conf/date/Ruiz-de-ClavijoJBAV01 export record as
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Irith Pomeranz ,
Sudhakar M. Reddy :
Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage.
504-508
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conf/date/WambacqVPREYLD01 export record as
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conf/date/Bazargan-SabetI01 export record as
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Youxin Gao ,
D. F. Wong :
A graph based algorithm for optimal buffer insertion under accurate delay models.
535-539
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conf/date/MacchiaruloBM01 export record as
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Bernhard Burdiek :
Generation of optimum test stimuli for nonlinear analog circuits using nonlinear - programming and time-domain sensitivities.
603-609
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Ron Wilson :
Managing the SoC design challenge with "Soft" hardware.
610-611
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Alex Doboli :
Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints.
612-619
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Yuan Xie ,
Wayne Wolf :
Allocation and scheduling of conditional task graph in hardware/software co-synthesis.
620-625
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Sri Parameswaran :
Code placement in hardware/software co-synthesis to improve performance and reduce cost.
626-632
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Iyad Ouaiss ,
Ranga Vemuri :
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers.
650-657
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Susumu Narita :
SH-4 RISC microprocessor for multimedia, game machine.
699-701
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Zhining Huang ,
Sharad Malik :
Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks.
735
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conf/date/Castro-LopezFDR01 export record as
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Jianwen Zhu :
Static memory allocation by pointer analysis and coloring.
785-790
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conf/date/ConstantinidesCL01 export record as
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conf/date/CasavantGLMWA01 export record as
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Alex Doboli ,
Ranga Vemuri :
A regularity-based hierarchical symbolic analysis method for large-scale analog networks.
806
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Franco Fiori :
Susceptibility of analog cells to substrate interference.
814
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