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ORCIDManuel Jesús Bellido Díaz
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- affiliation: University of Seville, Spain
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2020 – today
- 2023
[j13]German Cano-Quiveu
, Paulino Ruiz-De-Clavijo-Vazquez, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Julian Viejo-Cortes:
IRIS: An embedded secure boot for IoT devices. Internet Things 23: 100874 (2023)- 2021
- [j12]German Cano-Quiveu, Paulino Ruiz-De-Clavijo-Vazquez, Manuel Jesús Bellido Díaz, David Guerrero Martos, Julian Viejo-Cortes, Jorge Juan-Chico:
An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation. IEEE Access 9: 161383-161394 (2021) - 2020
- [j11]David Guerrero Martos, Alejandro Millán Calderón, Jorge Juan-Chico, Julian Viejo, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa:
Using the complement of the cosine to compute trigonometric functions. EURASIP J. Adv. Signal Process. 2020(1): 1-21 (2020) - [j10]David Guerrero Martos, German Cano-Quiveu, Jorge Juan-Chico, Alejandro Millán, Manuel J. Bellido, Julian Viejo, Paulino Ruiz-de-Clavijo, Enrique Ostúa:
Address-encoded byte order. Microprocess. Microsystems 78: 103268 (2020)
2010 – 2019
- 2017
- [j9]Paulino Ruiz-de-Clavijo, Enrique Ostúa, Manuel Jesús Bellido Díaz, Jorge Juan, Julian Viejo, David Guerrero Martos:
Minimalistic SDHC-SPI hardware reader module for boot loader applications. Microelectron. J. 67: 32-37 (2017) - 2016
- [j8]Juan Quiros, Sergey Verlan, Julian Viejo, Alejandro Millán, Manuel J. Bellido:
Fast Hardware Implementations of Static P Systems. Comput. Informatics 35(3): 687-718 (2016) - 2012
- [c26]Jorge Juan, Julian Viejo, Manuel J. Bellido:
Network Time Synchronization: A Full Hardware Approach. PATMOS 2012: 225-234 - 2011
- [j7]David Guerrero Martos, Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo:
Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. J. Low Power Electron. 7(3): 444-452 (2011) - [j6]Julian Viejo, Jorge Juan, Manuel Jesús Bellido Díaz, Alejandro Millán, Paulino Ruiz-de-Clavijo:
Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation. IEEE Trans. Instrum. Meas. 60(12): 3961-3963 (2011) - 2010
- [j5]Alejandro Millán, Manuel J. Bellido, Jorge Juan, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo:
Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies. J. Low Power Electron. 6(1): 93-102 (2010) - [c25]Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Manuel Jesús Bellido Díaz, Enrique Ostúa:
Design and implementation of a suitable core for on-chip long-term verification. SIES 2010: 234-237
2000 – 2009
- 2009
- [c24]Jose Ignacio Villar, Jorge Juan, Manuel J. Bellido:
Efficient techniques and methodologies for embedded system design usign free hardware and open standards. FPL 2009: 719-720 - 2008
- [c23]Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo:
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. PATMOS 2008: 389-398 - 2007
- [j4]David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo:
Improving the Performance of Static CMOS Gates by Using Independent Bodies. J. Low Power Electron. 3(1): 70-77 (2007) - [c22]David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo:
Static Power Consumption in CMOS Gates Using Independent Bodies. PATMOS 2007: 404-412 - [c21]Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Alejandro Muñoz:
Design of a FFT/IFFT module as an IP core suitable for embedded systems. SIES 2007: 337-340 - 2006
- [j3]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero Martos, Enrique Ostúa, Julian Viejo:
Accurate Logic-Level Current Estimation for Digital CMOS Circuits. J. Low Power Electron. 2(1): 87-94 (2006) - [c20]Julian Viejo, Manuel J. Bellido, Alejandro Millán, Enrique Ostúa, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos:
Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements. IES 2006: 1-7 - 2005
- [c19]Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Julian Viejo:
Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. PATMOS 2005: 337-347 - [c18]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo:
Logic-Level Fast Current Simulation for Digital CMOS Circuits. PATMOS 2005: 425-435 - 2004
- [c17]Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa:
Signal Sampling Based Transition Modeling for Digital Gates Characterization. PATMOS 2004: 829-837 - 2003
- [c16]Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Enrique Ostúa:
Internode: Internal Node Logic Computational Model. Annual Simulation Symposium 2003: 241-248 - [c15]David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán:
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. PATMOS 2003: 501-510 - 2002
- [c14]Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia:
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. PATMOS 2002: 353-362 - [c13]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán, David Guerrero Martos:
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. PATMOS 2002: 400-408 - [c12]Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos:
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). PATMOS 2002: 477-486 - [e1]Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido:
Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002. Lecture Notes in Computer Science 2451, Springer 2002, ISBN 3-540-44143-3 [contents] - 2001
- [c11]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero:
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE 2001: 467-471 - [c10]Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carmen Baena Oliva, Manuel Valencia:
AUTODDM: automatic characterization tool for the delay degradation model. ICECS 2001: 1631-1634 - [c9]Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero:
Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) 2001: 483-486 - 2000
- [c8]Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia:
Inertial and degradation delay model for CMOS logic gates. ISCAS 2000: 459-462 - [c7]Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero:
Degradation Delay Model Extension to CMOS Gates. PATMOS 2000: 149-158 - [c6]Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia-Barrero:
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. PATMOS 2000: 316-326
1990 – 1999
- 1998
- [c5]Raúl Jiménez, Antonio J. Acosta, Angel Barriga, Manuel J. Bellido, Manuel Valencia:
Efficient self-timed circuits based on weak NMOS-trees. ICECS 1998: 179-182 - 1996
- [c4]P. Fortet, Manuel J. Bellido, Francisco Sivianes, A. V. Medina:
Multimedia System for Instruction and Learning Electronics. CALISCE 1996: 442-444 - 1995
- [j2]Antonio J. Acosta, Manuel Valencia, Angel Barriga, Manuel J. Bellido, José L. Huertas:
SODS: a new CMOS differential-type structure. IEEE J. Solid State Circuits 30(7): 835-838 (1995) - [j1]Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano:
Modular Asynchronous Arbiter Insensitive to Metastability. IEEE Trans. Computers 44(12): 1456-1461 (1995) - [c3]Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas:
New CMOS VLSI linear self-timed architectures. ASYNC 1995: 14-23 - 1993
- [c2]Antonio J. Acosta, Angel Barriga, Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas:
Modeling of real bistables in VHDL. EURO-DAC 1993: 460-465 - [c1]Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro:
A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. ISCAS 1993: 2019-2022
Coauthor Index
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