ASP-DAC 2005: Shanghai, China

Keynote address

Tree construction and buffering

System level design methodology for network-on-chip

Test and DFT (1)


Clock, power grid and thermal analysis and optimization

Routing and interconnects

System level modeling and embedded software

Test and DFT (2)


Simulation and modeling techniques for RF/analog circuits

Logic synthesis

System level architecture design

Test and verification

Special Session

Placement techniques

Security processor design

(Special session) embedded tutorial II

(Special session) CAD for microarchitecture designs

University design contest

(Special session) embedded tutorial III

Design optimization for high-performance digital circuits

Floorplanning and partitioning

Advances in SAT technology and application

Analysis and simulation techniques

Interconnect modeling and analysis and system level design methodology

High-level synthesis

Low power

Formal verification: theory and practice

Special session

Robust and low-power clock design