"Measurements and analysis of SER-tolerant latch in a 90-nm ..."

Peter Hazucha et al. (2004)

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DOI: 10.1109/JSSC.2004.831449

access: closed

type: Journal Article

metadata version: 2022-04-27

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Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar:
Measurements and analysis of SER-tolerant latch in a 90-nm dual-V_T CMOS process. IEEE J. Solid State Circuits 39(9): 1536-1543 (2004)

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