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ORCIDN. P. van der Meijs
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- affiliation: Delft University of Technology, Netherlands
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2010 – 2019
- 2014
[j8]Qin Tang, Javier Rodríguez, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 210-223 (2014)- [j7]Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Considering Crosstalk Effects in Statistical Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 318-322 (2014) - [j6]Amir Zjajo, Nick van der Meijs, Rene van Leuken:
Dynamic Thermal Estimation Methodology for High-Performance 3-D MPSoC. IEEE Trans. Very Large Scale Integr. Syst. 22(9): 1920-1933 (2014) - [c36]Kristof Blutman, Jan A. Angevare, Amir Zjajo, Nick van der Meijs:
A 0.1pJ Freeze Vernier time-to-digital converter in 65nm CMOS. ISCAS 2014: 85-88 - [c35]Amir Zjajo, Nick van der Meijs, Rene van Leuken:
Statistical power optimization of deep-submicron digital CMOS circuits based on structured perceptron. ISIC 2014: 95-98 - 2013
- [j5]Amir Zjajo, Nick van der Meijs, Rene van Leuken:
Adaptive Thermal Monitoring of Deep-Submicron CMOS VLSI Circuits. J. Low Power Electron. 9(4): 403-413 (2013) - [c34]Amir Zjajo, Nick van der Meijs, Rene van Leuken:
Balanced stochastic truncation of coupled 3D interconnect. ICICDT 2013: 13-16 - [c33]Jan A. Angevare, Kristof Blutman, Amir Zjajo, Nick van der Meijs:
A CMOS 0.23pj Freeze Vernier Time-To-Digital Converter. NORCHIP 2013: 1-4 - 2012
- [c32]Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Crosstalk-aware statistical interconnect delay calculation. ASP-DAC 2012: 371-376 - [c31]Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Transistor-level gate model based statistical timing analysis considering correlations. DATE 2012: 917-922 - [c30]Amir Zjajo, Nick van der Meijs, René van Leuken:
A 11 µW 0°C-160°C temperature sensor in 90 nm CMOS for adaptive thermal monitoring of VLSI circuits. ISCAS 2012: 2007-2010 - [c29]Amir Zjajo, Nick van der Meijs, Rene van Leuken:
Thermal analysis of 3D integrated circuits based on discontinuous Galerkin finite element method. ISQED 2012: 117-222 - [c28]Javier Rodríguez, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Direct Statistical Simulation of Timing Properties in Sequential Circuits. PATMOS 2012: 131-141 - 2011
- [j4]Pieter Harpe, Cui Zhou, Yu Bi, N. P. van der Meijs, Xiaoyan Wang, Kathleen Philips, Guido Dolmans, Harmke de Groot:
A 26 μ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios. IEEE J. Solid State Circuits 46(7): 1585-1595 (2011) - [j3]Amir Zjajo, Qin Tang, Michel Berkelaar, José Pineda de Gyvez, Alessandro Di Bucchianico
, Nick van der Meijs:
Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(1): 164-175 (2011) - [c27]Yu Bi, Pieter Harpe, N. P. van der Meijs:
Efficient sensitivity-based capacitance modeling for systematic and random geometric variations. ASP-DAC 2011: 61-66 - [c26]Yu Bi, Simon de Graaf, Nick van der Meijs:
Enhanced sensitivity computation for BEM based capacitance extraction using the Schur complement technique. CICC 2011: 1-4 - [c25]Yu Bi, Kees-Jan van der Kolk, Jorge Fernandez Villena, Luís Miguel Silveira, Nick van der Meijs:
Fast statistical analysis of RC nets subject to manufacturing variabilities. DATE 2011: 31-37 - [c24]Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Pseudo circuit model for representing uncertainty in waveforms. DATE 2011: 1521-1524 - 2010
- [j2]Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Statistical Moment Estimation of Delay and Power in Circuit Simulation. J. Low Power Electron. 6(4): 578-587 (2010) - [c23]Amir Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs:
Noise analysis of non-linear dynamic integrated circuits. CICC 2010: 1-4 - [c22]Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
RDE-based transistor-level gate simulation for statistical static timing analysis. DAC 2010: 787-792 - [c21]Alejandro Viteri, Amir Zjajo, Thijmen Hamoen, Nick van der Meijs:
Digital cartesian feedback linearization of switched mode power amplifiers. ICECS 2010: 890-893 - [c20]Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations. PATMOS 2010: 190-199
2000 – 2009
- 2009
- [c19]Yu Bi, Kees-Jan van der Kolk, Nick van der Meijs:
Sensitivity computation using domain-decomposition for boundary element method based capacitance extractors. CICC 2009: 423-426 - [c18]Nuo Li, Nick van der Meijs:
A Radix 22 based parallel pipeline FFT processor for MB-OFDM UWB system. SoCC 2009: 383-386 - 2004
- [c17]Giuseppe S. Garcea, N. P. van der Meijs, Kees-Jan van der Kolk, Ralph H. J. M. Otten:
Statistically Aware Buffer Planning. DATE 2004: 1402-1403 - 2003
- [c16]Giuseppe S. Garcea, Nick van der Meijs, Ralph H. J. M. Otten:
Analytic model for area and power constrained optimal repeater insertion. ESSCIRC 2003: 591-594 - [c15]Giuseppe S. Garcea, N. P. van der Meijs, Ralph H. J. M. Otten:
Simultaneous Analytic Area and Power Optimization for Repeater Insertion. ICCAD 2003: 568-573 - 2002
- [c14]Eelco Schrik, N. P. van der Meijs:
Combined BEM/FEM substrate resistance modeling. DAC 2002: 771-776 - [c13]Eelco Schrik, Patrick M. Dewilde, N. P. van der Meijs:
Theoretical and practical validation of combined BEM/FEM substrate resistance modeling. ICCAD 2002: 10-15
1990 – 1999
- 1999
- [c12]A. J. Dammers, N. P. van der Meijs:
Virtual screening: a step towards a sparse partial inductance matrix. ICCAD 1999: 445-452 - 1997
- [c11]U. Geigenmüller, N. P. van der Meijs:
Cartesian multipole based numerical integration for 3D capacitance extraction. ED&TC 1997: 256-259 - 1996
- [c10]Arjan J. van Genderen, N. P. van der Meijs:
Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction. DAC 1996: 758-763 - [c9]P. J. H. Elias, N. P. van der Meijs:
Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency. DAC 1996: 764-769 - [c8]P. J. H. Elias, N. P. van der Meijs:
Including Higher-Order Moments of RC Interconnections in Layout-to-Circuit Extraction. ED&TC 1996: 362-367 - [c7]Arjan J. van Genderen, N. P. van der Meijs, T. Smedes:
Fast Computation of Substrate Resistances in Large Circuits. ED&TC 1996: 560-565 - [c6]N. P. van der Meijs, T. Smedes:
Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits. ICCAD 1996: 244-251 - 1995
- [c5]N. P. van der Meijs, Arjan J. van Genderen:
Delayed Frontal Solution for Finite-Element Based Resistance Extraction. DAC 1995: 273-278 - [c4]T. Smedes, N. P. van der Meijs, Arjan J. van Genderen:
Extraction of circuit models for substrate cross-talk. ICCAD 1995: 199-206 - [c3]Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs:
Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits. ICCD 1995: 360-365 - 1993
- [c2]Arjan J. van Genderen, N. P. van der Meijs:
Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures. ICCAD 1993: 764-769
1980 – 1989
- 1989
- [c1]N. P. van der Meijs, Arjan J. van Genderen:
An Efficient Finite Element Method for Submicron IC Capacitance Extraction. DAC 1989: 678-681 - 1984
- [j1]N. P. van der Meijs, J. T. Fokkema:
VLSI circuit reconstruction from mask topology. Integr. 2(2): 85-119 (1984)
Coauthor Index
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