Volume 31, Number 1, January 2012
Sachin S. Sapatnekar: Editorial. 1- Diana Marculescu, Peng Li: Guest Editorial Special Section on PAR-CAD: Parallel CAD Algorithms and CAD for Parallel Architectures/Systems. 7-8
- Nachiket Kapre, André DeHon: ${\rm SPICE}^2$: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA. 9-22
- Arvind Sridhar, Alessandro Vincenzi, Martino Ruggiero, David Atienza: Neural Network-Based Thermal Simulation of Integrated Circuits on GPUs. 23-36
- Jorge Fernandez Villena, Luis Miguel Silveira: Exploiting Parallelism for Improved Automation of Multidimensional Model Order Reduction. 37-49
- Marcel Gort, Jason Helge Anderson: Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010. 61-74
- Melinda Y. Agyekum, Steven M. Nowick: Error-Correcting Unordered Codes and Hardware Support for Robust Asynchronous Global Communication. 75-88
- Ibrahim N. Hajj: Extended Nodal Analysis. 89-100
- Yinghong Zhou, Emad Gad, Michel S. Nakhla, Ramachandra Achar: Structural Characterization and Efficient Implementation Techniques for $A$-Stable High-Order Integration Methods. 101-108
- Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong: A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints. 109-120
- Dukyoung Yun, Sungchan Kim, Soonhoi Ha: A Parallel Simulation Technique for Multicore Embedded Systems and Its Performance Analysis. 121-131
- Chengmo Yang, Alex Orailoglu: Tackling Resource Variations Through Adaptive Multicore Execution Frameworks. 132-145
- Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Memory-Efficient On-Chip Network With Adaptive Interfaces. 146-159
- Bing Shi, Yufu Zhang, Ankur Srivastava: Accelerating Gate Sizing Using Graphics Processing Units. 160-164
Volume 31, Number 2, February 2012
- Jiang Hu, Cheng-Kok Koh: Guest Editorial Special Section on the 2011 International Symposium on Physical Design. 165-166
- Kun Yuan, Bei Yu, David Z. Pan: E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters. 167-179
- Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak: ISPD11: Power-Driven Flip-Flop Merging and Relocation. 180-191
- Iris Hui-Ru Jiang, Chih-Long Chang, Yu-Ming Yang: INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving. 192-204
- Jianchao Lu, Xiaomi Mao, Baris Taskin: Integrated Clock Mesh Synthesis With Incremental Register Placement. 217-227
- Yang Zhao, Krishnendu Chakrabarty: Simultaneous Optimization of Droplet Routing and Control-Pin Mapping to Electrodes in Digital Microfluidic Biochips. 242-254
- Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze: Postgrid Clock Routing for High Performance Microprocessor Designs. 255-259
- Hratch Mangassarian, Andreas G. Veneris, Farid N. Najm: Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability. 271-284
- Carles Hernández, Antoni Roca, Federico Silla, Jose Flich, José Duato: On the Impact of Within-Die Process Variation in GALS-Based NoC Performance. 294-307
- Yen-Tzu Lin, Osei Poku, R. D. (Shawn) Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar: Physically-Aware N-Detect Test. 308-321
- Irith Pomeranz: Multipattern Scan-Based Test Sets With Small Numbers of Primary Input Sequences. 322-326
Volume 31, Number 3, March 2012
- Alireza Ejlali, Bashir M. Al-Hashimi, Petru Eles: Low-Energy Standby-Sparing for Hard Real-Time Systems. 329-342
- Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic: Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems. 343-355
- Mingzhi Gao, Zuochang Ye, Yan Wang, Zhiping Yu: Efficient Full-Chip Statistical Leakage Analysis Based on Fast Matrix Vector Product. 356-369
- Chun-Jen Wei, Howard Chen, Sao-Jie Chen: Design and Implementation of Block-Based Partitioning for Parallel Flip-Chip Power-Grid Analysis. 370-379
- Jongwon Lee, Duo Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Dan Jiao: A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits. 380-390
- Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori: Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors. 404-417
- Elena Kakoulli, Vassos Soteriou, Theocharis Theocharides: Intelligent Hotspot Prediction for Network-on-Chip-Based Multicore Systems. 418-431
- Paolo Maffezzoni: Stochastic Analysis of Switched-Capacitor Circuits for Sampled Data Converters. 432-436
- Zhuo Li, Ying Zhou, Weiping Shi: $O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets With $m$ Sinks. 437-441
- Joon-Sung Yang, Nur A. Touba: Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis. 442-446
- Sourasis Das, Ansuman Banerjee, Pallab Dasgupta: Early Analysis of Critical Faults: An Approach to Test Generation From Formal Specifications. 447-451
- Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong: Corrigendum to "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints". 452
Volume 31, Number 4, April 2012
- Jie Zhang, Albert Lin, Nishant Patil, Hai Wei, Lan Wei, H.-S. Philip Wong, Subhasish Mitra: Carbon Nanotube Robust Digital VLSI. 453-471
- Khaled R. Heloue, Sari Onaissi, Farid N. Najm: Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths. 472-484
- Jaeyong Chung, Jacob A. Abraham: Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA. 485-496
- Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham: Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator. 497-508
- Walid Ibrahim, Valeriu Beiu, Azam Beg: GREDA: A Fast and More Accurate Gate Reliability EDA Tool. 509-521
- Tom J. Kazmierski, Leran Wang, Bashir M. Al-Hashimi, Geoff V. Merrett: An Explicit Linearized State-Space Technique for Accelerated Simulation of Electromagnetic Vibration Energy Harvesters. 522-531
- Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Guoyong Shi, Grantham K. H. Pang, Ngai Wong: Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation. 532-545
- Hyungmin Cho, Larkhoon Leem, Subhasish Mitra: ERSA: Error Resilient System Architecture for Probabilistic Applications. 546-558
- Hyunsun Park, Sungjoo Yoo, Sunggu Lee: A Multistep Tag Comparison Method for a Low-Power L2 Cache. 559-572
- Giorgos Passas, Manolis Katevenis, Dionisios N. Pnevmatikatos: Crossbar NoCs Are Scalable Beyond 100 Nodes. 573-585
- Sonali Chouhan, M. Balakrishnan, Ranjan Bose: System-Level Design Space Exploration Methodology for Energy-Efficient Sensor Node Configurations: An Experimental Validation. 586-596
- Hao-Chiao Hong: A Static Linear Behavior Analog Fault Model for Switched-Capacitor Circuits. 597-609
- Shyue-Kung Lu, Zhen-Yu Wang, Yi-Ming Tsai, Jiann-Liang Chen: Efficient Built-In Self-Repair Techniques for Multiple Repairable Embedded RAMs. 620-629
- Hongxia Fang, Krishnendu Chakrabarty, Zhiyuan Wang, Xinli Gu: Reproduction and Detection of Board-Level Functional Failure. 630-643
- Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Cheng-Ho Chang: $2^{n}$ Pattern Run-Length for Test Data Compression. 644-648
Volume 31, Number 5, May 2012
- Xin Jin, Satoshi Goto: Hilbert Transform-Based Workload Prediction and Dynamic Frequency Scaling for Power-Efficient Video Encoding. 649-661
- Lu Wan, Deming Chen: Analysis of Digital Circuit Dynamic Behavior With Timed Ternary Decision Diagrams for Better-Than-Worst-Case Design. 662-675
- Samson Melamed, Thorlindur Thorolfsson, T. Robert Harris, Shivam Priyadarshi, Paul D. Franzon, Michael B. Steer, W. Rhett Davis: Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring. 676-689
- Abde Ali Kagalwalla, Puneet Gupta, Christopher J. Progler, Steve McDonald: Design-Aware Mask Inspection. 690-702
- Shao-Yun Fang, Szu-Yu Chen, Yao-Wen Chang: Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology. 703-716
- Hassan Salamy, J. Ramanujam: An Effective Solution to Task Scheduling and Memory Partitioning for Multiprocessor System-on-Chip. 717-725
- Andrew DeOrio, David Fick, Valeria Bertacco, Dennis Sylvester, David Blaauw, Jin Hu, Gregory K. Chen: A Reliable Routing Architecture and Algorithm for NoCs. 726-739
- Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano: OSCAR: An Optimization Methodology Exploiting Spatial Correlation in Multicore Design Spaces. 740-753
- Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer: Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement. 754-764
- Hana Chockler, Daniel Kroening, Mitra Purandare: Computing Mutation Coverage in Interpolation-Based Model Checking. 765-778
- Tobias Welp, Nathan Kitchen, Andreas Kuehlmann: Hardware Acceleration for Constraint Solving for Random Simulation. 779-789
- Lingyi Liu, David Sheridan, William Tuohy, Shobha Vasudevan: A Technique for Test Coverage Closure Using GoldMine. 790-803
- Yao-Lin Jiang, Hai-Bao Chen: Application of General Orthogonal Polynomials to Fast Simulation of Nonlinear Descriptor Systems Through Piecewise-Linear Approximation. 804-808
- Elif Alpaslan, Bram Kruseman, Ananta K. Majhi, Wilmar M. Heuvelman, Jennifer Dworak: NIM-X: A Noise Index Model-Based X-Filling Technique to Overcome the Power Supply Switching Noise Effects on Path Delay Test. 809-813
Volume 31, Number 6, June 2012
- Yang Zhao, Krishnendu Chakrabarty: Cross-Contamination Avoidance for Droplet Routing in Digital Microfluidic Biochips. 817-830
- Xue-Yang Zhu, Twan Basten, Marc Geilen, Sander Stuijk: Efficient Retiming of Multirate DSP Algorithms. 831-844
- Mu-Shun Matt Lee, Wei-Ting Liao, Chien-Nan Jimmy Liu: Levelized High-Level Current Model of Logic Blocks for Dynamic Supply Noise Analysis. 845-857
- Komail M. H. Badami, Shreepad Karmalkar: Quasi-Static Compact Model for Coupling Between Aligned Contacts on Finite Substrates With Insulating or Conducting Backplanes. 858-867
- Haifeng Qian, Phillip J. Restle, Joseph N. Kozhaya, Clifford L. Gunion: Subtractive Router for Tree-Driven-Grid Clocks. 868-877
- Chung-Wei Lin, Po-Wei Lee, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng: An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs. 878-889
- Pengju Ren, Mieszko Lis, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Nanning Zheng, Srinivas Devadas: HORNET: A Cycle-Level Multicore Simulator. 890-903
- Jin Cui, Douglas L. Maskell: A Fast High-Level Event-Driven Thermal Estimator for Dynamic Thermal Aware Scheduling. 904-917
- Wing Chiu Tam, R. D. (Shawn) Blanton: SLIDER: Simulation of Layout-Injected Defects for Electrical Responses. 918-929
- Ting-Ju Chen, Jin-Fu Li, Tsu-Wei Tseng: Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs. 930-940
- Gurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian: A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs. 941-949
- Thomas Rabenalt, Michael Richter, Frank Poehl, Michael Gössel: Highly Efficient Test Response Compaction Using a Hierarchical X-Masking Technique. 950-957
- Afsaneh Nassery, Osman Emir Erol, Sule Ozev, Marian Verhelst: Test Signal Development and Analysis for OFDM Systems RF Front-End Parameter Extraction. 958-967
- Ender Yilmaz, Sule Ozev: Test Application for Analog/RF Circuits With Low Computational Burden. 968-979
Volume 31, Number 7, July 2012
- Bo Liu, Noël Deferm, Dixian Zhao, Patrick Reynaert, Georges G. E. Gielen: An Efficient High-Frequency Linear RF Amplifier Synthesis Method Based on Evolutionary Computation and Machine Learning Techniques. 981-993
- Xiangyu Dong, Cong Xu, Yuan Xie, Norman P. Jouppi: NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. 994-1007
- Lin Xie, Azadeh Davoodi: Post-Silicon Failing-Path Isolation Incorporating the Effects of Process Variations. 1008-1018
- Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin: Clock Gating Synthesis of Pulsed-Latch Circuits. 1019-1030
- Quan Chen, Shih-Hung Weng, Chung-Kuan Cheng: A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation. 1031-1040
- Ming-Chao Lee, Yiyu Shi, Shih-Chieh Chang: Efficient Wakeup Scheduling Considering Both Resource Usage and Timing Budget for Power Gating Designs. 1041-1049
- Chih-Hung Liu, Sy-Yen Kuo, D. T. Lee, Chun-Syun Lin, Jung-Hung Weng, Shih-Yi Yuan: Obstacle-Avoiding Rectilinear Steiner Tree Construction: A Steiner-Point-Based Algorithm. 1050-1060
- Turbo Majumder, Michael Edward Borgens, Partha Pratim Pande, Ananth Kalyanaraman: On-Chip Network-Enabled Multicore Platforms Targeting Maximum Likelihood Phylogeny Reconstruction. 1061-1073
- Hao Shen, Mian Muhammad Hamayun, Frédéric Pétrot: Native Simulation of MPSoC Using Hardware-Assisted Virtualization. 1074-1087
- Vishwanath Natarajan, Hyun Woo Choi, Aritra Banerjee, Shreyas Sen, Abhijit Chatterjee, Ganesh Srinivasan, Friedrich Taenzler, Soumendu Bhattacharya: Low Cost EVM Testing of Wireless RF SoC Front-Ends Using Multitones. 1088-1101
- Haralampos-G. D. Stratigopoulos: Test Metrics Model for Analog Test Development. 1116-1128
- Jussi H. Poikonen, Eero Lehtonen, Mika Laiho: On Synthesis of Boolean Expressions for Memristive Devices Using Sequential Implication Logic. 1129-1134
- Yu-Yi Liang, Tien-Yu Kuo, Shao-Huan Wang, Wai-Kei Mak: ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules. 1134-1139
- Tom Smy, Pavan K. Gunupudi: Robust Simulation of Opto-Electronic Systems by Alternating Complex Envelope Representations. 1139-1143
Volume 31, Number 8, August 2012
- Xiaoke Qin, Weixun Wang, Prabhat Mishra: TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking Systems. 1159-1168
- Byeong Yong Kong, In-Cheol Park: FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis. 1169-1179
- Shih-Hung Weng, Quan Chen, Chung-Kuan Cheng: Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control. 1180-1193
- Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim: TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC. 1194-1207
- Xin Zhao, Jeremy R. Tolbert, Saibal Mukhopadhyay, Sung Kyu Lim: Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits. 1222-1234
- Arseniy Vitkovskiy, Vassos Soteriou, Chrysostomos Nicopoulos: A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant Mechanism for NoCs. 1235-1248
- Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham: Testability-Driven Statistical Path Selection. 1275-1287
- ShengYu Shen, Ying Qin, KeFei Wang, Zhengbin Pang, Jianmin Zhang, Sikun Li: Inferring Assertion for Complementary Synthesis. 1288-1292
- Eric A. Foreman, Peter A. Habitz, Ming-C. Cheng, Chandu Visweswariah: A Novel Method for Reducing Metal Variation With Statistical Static Timing Analysis. 1293-1297
- Allon Adir, Amir Nahir, Avi Ziv: Concurrent Generation of Concurrent Programs for Post-Silicon Validation. 1297-1302
Volume 31, Number 9, September 2012
- Chirag Ravishankar, Jason Helge Anderson, Andrew A. Kennings: FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture. 1305-1318
- Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, Jie-Hong R. Jiang: Automatic Decoder Synthesis: Methods and Case Studies. 1319-1331
- Parijat Mukherjee, G. Peter Fang, Rod Burt, Peng Li: Efficient Identification of Unstable Loops in Large Linear Analog Integrated Circuits. 1332-1345
- Angelo Brambilla, Giambattista Gruosso, Giancarlo Storti Gajani: MTFS: Mixed Time-Frequency Method for the Steady-State Analysis of Almost-Periodic Nonlinear Circuits. 1346-1355
- Qiang Ma, Martin D. F. Wong: NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing. 1356-1365
- Meng-Kai Hsu, Yao-Wen Chang: Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs. 1366-1378
- Rani S. Ghaida, Puneet Gupta: DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies. 1379-1392
- Joon-Sung Yang, Nur A. Touba: X-Canceling MISR Architectures for Output Response Compaction With Unknown Values. 1417-1427
- Irith Pomeranz: Multicycle Tests With Constant Primary Input Vectors for Increased Fault Coverage. 1428-1438
- Ansuman Banerjee: Verifying Coalitions in 3-Party Systems. 1439-1451
- Jyotirmoy Ghosh, Siddhartha Mukhopadhyay, Amit Patra, Barry Culpepper, Tawen Mei: Estimation of dc Performance of a Lateral Power MOSFET Using Distributed Cell Model. 1452-1456
- Hubert Filiol, Ian O'Connor, Dominique Morche: Analog IC Variability Bound Estimation Using the Cornish-Fisher Expansion. 1457-1461
Volume 31, Number 10, October 2012
- Massoud Pedram: Energy-Efficient Datacenters. 1465-1484
- Ashish Kumar Singh, Kareem Ragab, Mario Lok, Constantine Caramanis, Michael Orshansky: Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics. 1485-1498
- Salvatore Levantino, Paolo Maffezzoni: Computing the Perturbation Projection Vector of Oscillators via Frequency Domain Analysis. 1499-1507
- Rohit Sinha, Hiren D. Patel: synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs. 1508-1521
- Shivam Priyadarshi, Christopher S. Saunders, Nikhil Kriplani, Harun Demircioglu, W. Rhett Davis, Paul D. Franzon, Michael B. Steer: Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning. 1522-1535
- Dongchul Kim, Hyewon Kim, Yungseon Eo: Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Single Interconnect Lines. 1536-1545
- Kai-Ti Hsu, Subarna Sinha, Yu-Chuan Pi, Tsung-Yi Ho: A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations. 1546-1557
- Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu: Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs. 1558-1571
- Jens Gladigau, Christian Haubelt, Jürgen Teich: Model-Based Virtual Prototype Acceleration. 1572-1585
- Hongxia Fang, Krishnendu Chakrabarty, Zhiyuan Wang, Xinli Gu: Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster-Shafer Theory. 1586-1599
- Xiaochun Yu, Ronald D. Blanton: Improving Diagnosis Through Failing Behavior Identification. 1614-1625
Volume 31, Number 11, November 2012
- Timothée Levi, Noëlle Lewis, Jean Tomas, Sylvie Renaud: Application of IP-Based Analog Platforms in the Design of Neuromimetic Integrated Circuits. 1629-1641
- Dogan Fennibay, Arda Yurdakul, Alper Sen: A Heterogeneous Simulation and Modeling Framework for Automation Systems. 1642-1655
- Yi-Ling Hsieh, Tsung-Yi Ho, Krishnendu Chakrabarty: A Reagent-Saving Mixing Algorithm for Preparing Multiple-Target Biochemical Samples Using Digital Microfluidics. 1656-1669
- Bing Li, Ning Chen, Ulf Schlichtmann: Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations. 1670-1683
- Jongyoon Jung, Taewhan Kim: Variation-Aware False Path Analysis Based on Statistical Dynamic Timing Analysis. 1684-1697
- Chuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee: Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates. 1698-1710
- Wai-Kei Mak, Yu-Chen Lin, Chris Chu, Ting-Chi Wang: Pad Assignment for Die-Stacking System-in-Package Design. 1711-1722
- Kuan-Hsien Ho, Jie-Hong Roland Jiang, Yao-Wen Chang: TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders. 1723-1733
- Irith Pomeranz: A Metric for Identifying Detectable Path Delay Faults. 1734-1742
- Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji: Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands. 1754-1766
- Dongkeun Oh, Charlie Chung-Ping Chen, Yu Hen Hu: Efficient Thermal Simulation for 3-D IC With Thermal Through-Silicon Vias. 1767-1771
- Subhankar Mukherjee, Pallab Dasgupta: Assertion Aware Sampling Refinement: A Mixed-Signal Perspective. 1772-1776
- Subhankar Mukherjee, Pallab Dasgupta: Computing Minimal Debugging Windows in Failure Traces of AMS Assertions. 1776-1781
- Rupesh S. Shelar: A Fast and Near-Optimal Clustering Algorithm for Low-Power Clock Tree Synthesis. 1781-1786
Volume 31, Number 12, December 2012
- Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang: Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors. 1789-1802
- Giovanni Ansaloni, Kazuyuki Tanimura, Laura Pozzi, Nikil Dutt: Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays. 1803-1816
- Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, José M. Mendías, María C. Molina: Multispeculative Addition Applied to Datapath Synthesis. 1817-1830
- Shupeng Sun, Yamei Feng, Changdao Dong, Xin Li: Efficient SRAM Failure Rate Prediction via Gibbs Sampling. 1831-1844
- Zahra Lak, Nicola Nicolici: On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging. 1845-1856
- Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang: Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification. 1857-1866
- Sudarshan Srinivasan, Kunal P. Ganeshpure, Sandip Kundu: A Wavelet-Based Spatio-Temporal Heat Dissipation Model for Reordering of Program Phases to Produce Temperature Extremes in a Chip. 1867-1880
- Nicolas G. Constantin, Kai H. Kwok, Hongxiao Shao, Cristian Cismaru, Peter J. Zampardi: Formulations and a Computer-Aided Test Method for the Estimation of IMD Levels in an Envelope Feedback RFIC Power Amplifier. 1881-1893
- Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: EDT Bandwidth Management in SoC Designs. 1894-1907
- Michael A. Kochte, Melanie Elm, Hans-Joachim Wunderlich: Accurate X-Propagation for Test Applications by SAT-Based Reasoning. 1908-1919
- Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts: Statistical Compact Model Extraction: A Neural Network Approach. 1920-1924
- Paolo Maffezzoni, Salvatore Levantino: Phase-Noise Analysis and Simulation of LC Oscillator-Based Injection-Locked Frequency Dividers. 1925-1929
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2013-06-18T214307 by the dblp team