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Meng-Kai Hsu
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2010 – 2019
- 2014
- [j3]Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Sheng Chou, Tzu-Hen Lin, Tung-Chieh Chen, Yao-Wen Chang:
NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1914-1927 (2014) - [c7]Meng-Kai Hsu, Nitesh Katta, Homer Yen-Hung Lin, Keny Tzu-Hen Lin, King Ho Tam, Ken Chung-Hsing Wang:
Design and manufacturing process co-optimization in nano-technology. ICCAD 2014: 574-581 - 2013
- [j2]Meng-Kai Hsu, Valeriy Balabanov, Yao-Wen Chang:
TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(4): 497-509 (2013) - [c6]Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Tung-Chieh Chen, Yao-Wen Chang:
Routability-driven placement for hierarchical mixed-size circuit designs. DAC 2013: 151:1-151:6 - 2012
- [j1]Meng-Kai Hsu, Yao-Wen Chang:
Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(9): 1366-1378 (2012) - [c5]Sheng Chou, Meng-Kai Hsu, Yao-Wen Chang:
Structure-aware placement for datapath-intensive circuit designs. DAC 2012: 762-767 - 2011
- [c4]Meng-Kai Hsu, Yao-Wen Chang, Valeriy Balabanov:
TSV-aware analytical placement for 3D IC designs. DAC 2011: 664-669 - [c3]Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, Yao-Wen Chang:
Routability-driven analytical placement for mixed-size circuit designs. ICCAD 2011: 80-84 - 2010
- [c2]Meng-Kai Hsu, Yao-Wen Chang:
Unified analytical global placement for large-scale mixed-size circuit designs. ICCAD 2010: 657-662
2000 – 2009
- 2009
- [c1]Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao:
Spare-cell-aware multilevel analytical placement. DAC 2009: 430-435
Coauthor Index
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