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Hua-Yu Chang

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2020 – today

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2022
[c12]
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  - conf/ispd/LiuCCLL22
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Wen-Hao Liu, Bing Chen, Hua-Yu Chang, Gary Lin, Zi-Shen Lin:
Challenges for Automating Package Routing. ISPD 2022: 193-194

2010 – 2019

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2019
[c11]
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Hua-Yu Chang, Iris Hui-Ru Jiang:
Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement. ISPD 2019: 93-100
2018
[c10]
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Iris Hui-Ru Jiang, Hua-Yu Chang:
Recent Research and Challenges in Multiple Patterning Layout Decomposition. ISVLSI 2018: 498-499
2017
[j6]
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Iris Hui-Ru Jiang, Hua-Yu Chang:
Multiple Patterning Layout Decomposition Considering Complex Coloring Rules and Density Balancing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12): 2080-2092 (2017)
2016
[c9]
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Hua-Yu Chang, Iris Hui-Ru Jiang:
Multiple patterning layout decomposition considering complex coloring rules. DAC 2016: 40:1-40:6
2015
[j5]
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Hua-Yu Chang, Iris Hui-Ru Jiang, H. Peter Hofstee, Damir A. Jamsek, Gi-Joon Nam:
Feature detection for image analytics via FPGA acceleration. IBM J. Res. Dev. 59(2/3) (2015)
2014
[c8]
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Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Functional ECO Using Metal-Configurable Gate-Array Spare Cells. DAC 2014: 191:1-191:6
[c7]
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Iris Hui-Ru Jiang, Gi-Joon Nam, Hua-Yu Chang, Sani R. Nassif, Jerry Hayes:
Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations. ICCAD 2014: 382-388
2013
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Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
ECO Optimization Using Metal-Configurable Gate-Array Spare Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1722-1733 (2013)
2012
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Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1857-1866 (2012)
[j2]
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Iris Hui-Ru Jiang, Hua-Yu Chang:
ECOS: Stable Matching Based Metal-Only ECO Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 485-497 (2012)
[j1]
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Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang:
WiT: Optimal Wiring Topology for Electromigration Avoidance. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 581-592 (2012)
[c6]
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Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Timing ECO optimization using metal-configurable gate-array spare cells. DAC 2012: 802-807
2011
[c5]
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Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Simultaneous functional and timing ECO. DAC 2011: 140-145
[c4]
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Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Timing ECO optimization via Bézier curve smoothing and fixability identification. ICCAD 2011: 742-746
2010
[c3]
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Iris Hui-Ru Jiang, Hua-Yu Chang:
Live Demo: ECOS 1.0: A metal-only ECO synthesizer. ISCAS 2010: 2774
[c2]
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Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang:
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles. ISPD 2010: 177-184

2000 – 2009

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2009
[c1]
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Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, Huang-Bi Hung:
Matching-based minimum-cost spare cell selection for design changes. DAC 2009: 408-411

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