Volume 20, Number 1, January 2001
Maria del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee: Optimal design of a CMOS op-amp via geometric programming. 1-21- Mayukh Bhattacharya, Pinaki Mazumder: Augmentation of SPICE for simulation of circuits containingresonant tunneling diodes. 39-50
- Rolf Drechsler, Wolfgang Günther, Fabio Somenzi: Using lower bounds during dynamic BDD minimization. 51-57
- Hirendu Vaishnav, Massoud Pedram: Alphabetic trees-theory and applications in layout-driven logicsynthesis. 58-69
- Michael W. Beattie, Byron Krauter, Lale Alatan, Lawrence T. Pileggi: Equipotential shells for efficient inductance extraction. 70-79
- Mohamed Hafed, Mourad Oulmane, Nicholas C. Rumin: Delay and current estimation in a CMOS inverter with an RC load. 80-89
- Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay: Interconnect synthesis without wire tapering. 90-104
- Tom J. Smy, David J. Walkey, Steven K. Dew: A 3D thermal simulation tool for integrated devices-Atar. 105-115
- André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand: On the detectability of CMOS floating gate transistor faults. 116-128
- Wendy Belluomini, Chris J. Myers, H. Peter Hofstee: Timed circuit verification using TEL structures. 129-146
- Shih-Chieh Chang, Jiann-Chyi Rau: A timing-driven pseudoexhaustive testing for VLSI circuits. 147-158
- Kamal S. Khouri, Niraj K. Jha: Clock selection for performance optimization of control-flowintensive behaviors. 158-165
- Yun-Che Wen, Kuen-Jong Lee: Analysis and generation of control and observation structures foranalog circuits. 165-171
- Yi-Jong Yeh, Sy-Yen Kuo, Jing-Yang Jou: Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design. 172-176
Volume 20, Number 2, February 2001
- Praveen K. Murthy, Shuvra S. Bhattacharyya: Shared buffer implementations of signal processing systems usinglifetime analysis techniques. 177-198
- Sanghun Park, Kiyoung Choi: Performance-driven high-level synthesis with bit-level chaining andclock selection. 199-212
- Luc Séméria, Giovanni De Micheli: Resolution, optimization, and encoding of pointer variables for thebehavioral synthesis from C. 213-233
- Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton: Theory of safe replacements for sequential circuits. 249-265
- Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang: Charge-sharing alleviation and detection for CMOS domino circuits. 266-280
- Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng, Takeshi Yoshimura: Floorplanning using a tree representation. 281-289
- Hyungwon Kim, John P. Hayes: Realization-independent ATPG for designs with unimplemented blocks. 290-306
- Khaled Saab, Naim Ben Hamida, Bozena Kaminska: Closing the gap between analog and digital testing. 307-314
- Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah, John P. Hayes: Fast and accurate timing characterization using functionalinformation. 315-331
- Adnan Aziz, James H. Kukula, Thomas R. Shiple, Jun Yuan: Efficient control state-space search. 332-336
- Irith Pomeranz, Sudhakar M. Reddy: Vector replacement to improve static-test compaction forsynchronous sequential circuits. 336-342
- Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Kun-Lin Tsai: A bipartition-codec architecture to reduce power in pipelinedcircuits. 343-348
Volume 20, Number 3, March 2001
- Ramesh Karri: Guest editor's introduction to special section on high-level design validation and test. 353-354
- Anshuman Chandra, Krishnendu Chakrabarty: System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes. 355-368
- Chung-Yang Huang, Kwang-Ting Cheng: Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking. 381-391
- Farinaz Koushanfar, Darko Kirovski, Inki Hong, Miodrag Potkonjak, Marios C. Papaefthymiou: Symbolic debugging of embedded hardware and software. 392-401
- Indradeep Ghosh, Masahiro Fujita: Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams. 402-415
- Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng: Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects. 416-425
- Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha: Testing of core-based systems-on-a-chip. 426-439
- Mukund Sivaraman, Andrzej J. Strojwas: Path delay fault diagnosis and coverage-a metric and an estimationtechnique. 440-457
- Clayton B. McDonald, Randal E. Bryant: CMOS circuit verification with symbolic switch-level timingsimulation. 458-474
Volume 20, Number 4, April 2001
- Siddharth Rele, Vipin Jain, Santosh Pande, J. Ramanujam: Compact and efficient code generation through program restructuringon limited memory embedded DSPs. 477-494
- Yutao Ma, Litian Liu, Lilin Tian, Zhiping Yu, Zhijian Li: Analytical charge-control and I-V model for submicrometer anddeep-submicrometer MOSFETs fully comprising quantum mechanical effects. 495-502
- Prashant Saxena, C. L. Liu: Optimization of the maximum delay of global interconnects duringlayer assignment. 503-515
- Lixin Su, Wray L. Buntine, A. Richard Newton, Bradley S. Peters: Learning as applied to stochastic optimization for standard-cellplacement. 516-527
- Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers, blockages, and bays. 556-562
Volume 20, Number 5, May 2001
- Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap: RC delay metrics for performance optimization. 571-582
- Evanthia Papadopoulou: Critical area computation for missing material defects in VLSIcircuits. 583-597
- Lauren Hui Chen, Malgorzata Marek-Sadowska: Aggressor alignment for worst-case crosstalk noise. 612-621
- Christoph Albrecht: Global routing by new approximation algorithms for multicommodityflow. 622-632
- Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt: Toward accurate models of achievable routing. 648-659
- Probir Sarkar, Cheng-Kok Koh: Routability-driven repeater block planning for interconnect-centricfloorplanning. 660-671
- Rony Kay, Rob A. Rutenbar: Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution. 672-679
- Yu-Yen Mo, Chris C. N. Chu: Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization. 680-686
- Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong: Handling soft modules in general nonslicing floorplan usingLagrangian relaxation. 687-692
Volume 20, Number 6, June 2001
- Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh: Activity-driven clock design. 705-714
- Amr G. Wassal, M. Anwar Hasan: Low-power system-level design of VLSI packet switching fabrics. 723-738
- Jason Cong, David Zhigang Pan: Interconnect performance estimation models for design planning. 739-752
- Peter Meuris, Wim Schoenmaker, Wim Magnus: Strategy for electromagnetic interconnect modeling. 753-762
- Junlin Zhou, Mengzhang Cheng, Leonard Forbes: SPICE models for flicker noise in p-MOSFETs in the saturationregion. 763-767
- Kanishka Lahiri, Anand Raghunathan, Sujit Dey: System-level performance analysis for designing on-chipcommunication architectures. 768-783
- Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong: Matching-based algorithm for FPGA channel segmentation design. 784-791
- Irith Pomeranz, Sudhakar M. Reddy: On diagnosis and diagnostic test generation for pattern-dependenttransition faults. 791-800
- Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. 800-807
Volume 20, Number 7, July 2001
- C.-J. Richard Shi, Sheldon X.-D. Tan: Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design. 813-827
- Zaher Baidas, Andrew D. Brown, Alan Christopher Williams: Floating-point behavioral synthesis. 828-839
- Tajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli: Event-driven power management. 840-857
- Kyu-Il Lee, Jinsoo Kim, Young June Park, Hong Shick Min: Simple frequency-domain analysis of MOSFET-includingnonquasi-static effect. 867-876
- Phillip Restle, Albert E. Ruehli, Steven G. Walker, George Papadopoulos: Full-wave PEEC time-domain method for the modeling of on-chipinterconnects. 877-886
- Kenneth L. Shepard, Dae-Jin Kim: Body-voltage estimation in digital PD-SOI circuits and itsapplication to static timing analysis. 888-901
- Ruiqi Tian, Martin D. F. Wong, Robert Boone: Model-based dummy feature placement for oxide chemical-mechanicalpolishing manufacturability. 902-910
- Tsung-Chu Huang, Kuen-Jong Lee: Reduction of power consumption in scan-based circuits during testapplication by an input control technique. 911-917
Volume 20, Number 8, August 2001
- Ki-Il Kum, Wonyong Sung: Combined word-length optimization and high-level synthesis ofdigital signal processing systems. 921-930
- Qing Wu, Qinru Qiu, Massoud Pedram: Estimation of peak power dissipation in VLSI circuits using thelimiting distributions of extreme order statistics. 942-956
- Angelo Brambilla, Paolo Maffezzoni: Statistical method for the analysis of interconnects delay insubmicrometer layouts. 957-966
- Lih-Yang Wang, Yen-Tai Lai: Graph-theory-based simplex algorithm for VLSI layout spacingproblems with multiple variable constraints. 967-979
- Irith Pomeranz, Y. Zonan: Testing of scan circuits containing nonisolated random-logic legacycores. 980-993
- Farzan Fallah, Srinivas Devadas, Kurt Keutzer: Functional vector generation for HDL models using linearprogramming and Boolean satisfiability. 994-1002
- Farzan Fallah, Srinivas Devadas, Kurt Keutzer: OCCOM-efficient computation of observability-based code coveragemetrics for functional verification. 1003-1015
- Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli: Synchronous approach to the functional equivalence of embeddedsystem implementations. 1016-1033
Volume 20, Number 9, September 2001
- Geert Van der Plas, Geert Debyser, Francky Leyn, Koen Lampaert, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen, Petar Veselinovic, Domine Leenaerts: AMGIE-A synthesis environment for CMOS analog integrated circuits. 1037-1058
- Luca P. Carloni, Kenneth L. McMillan, Alberto L. Sangiovanni-Vincentelli: Theory of latency-insensitive design. 1059-1076
- Jason Cong, Yean-Yow Hwang: Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping. 1077-1090
- Arlindo L. Oliveira: Techniques for the creation of digital watermarks in sequentialcircuit designs. 1101-1117
- Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino: Synthesis of power-managed sequential components based oncomputational kernel extraction. 1118-1131
- Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian: Switching activity generation with automated BIST synthesis forperformance testing of interconnects. 1143-1158
- Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Interconnect sizing and spacing with consideration of couplingcapacitance. 1164-1169
- Radomir S. Stankovic, Tsutomu Sasao: A discussion on the history of research in arithmetic andReed-Muller expressions. 1177-1179
Volume 20, Number 10, October 2001
- Wim F. J. Verhaegh, Emile H. L. Aarts, Paul C. N. van Gorp, Paul E. R. Lippens: A two-stage solution approach to multidimensional periodicscheduling. 1185-1199
- Qinru Qiu, Q. Qu, Massoud Pedram: Stochastic modeling of a power-managed system-construction andoptimization. 1200-1217
- Zilu Wu, Yumin Gao, Jinsheng Luo, Xun Hou, Guofu Chen: Application of BEM to high-voltage junction termination. 1218-1225
- Pankaj Pant, Yuan-Chieh Hsu, Sandeep K. Gupta, Abhijit Chatterjee: Path delay fault diagnosis in combinational circuits with implicitfault enumeration. 1226-1235
- Andrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe: Constraint-based watermarking techniques for design IP protection. 1236-1252
- John Lach, William H. Mangione-Smith, Miodrag Potkonjak: Fingerprinting techniques for field-programmable gate arrayintellectual property protection. 1253-1261
- Irith Pomeranz, Sudhakar M. Reddy: Forward-looking fault simulation for improved static compaction. 1262-1265
- Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang: Generic ILP-based approaches for time-multiplexed FPGA partitioning. 1266-1274
Volume 20, Number 11, November 2001
- Peter Marwedel: Guest editorial. 1281-1282
- Andrea Acquaviva, Luca Benini, Bruno Riccò: Software-controlled processor speed setting for low-power streamingmultimedia. 1283-1292
- Lovic Gauthier, Sungjoo Yoo, Ahmed Amine Jerraya: Automatic generation and targeting of application-specificoperating systems and embedded systems software. 1293-1301
- Peter Petrov, Alex Orailoglu: Performance and power effectiveness in embedded processors customizable partitioned caches. 1309-1318
- Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama: A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. 1319-1328
- Lars Wehmeyer, Manoj Kumar Jain, Stefan Steinke, Peter Marwedel, M. Balakrishnan: Analysis of the influence of register file size on energyconsumption, code size, and execution time. 1329-1337
- Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr: A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. 1338-1354
- Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood: Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. 1355-1371
Volume 20, Number 12, December 2001
- Roberto Cordone, Fabrizio Ferrandi, Donatella Sciuto, Roberto Wolfler Calvo: An efficient heuristic approach to solve the unate covering problem. 1377-1388
- Giorgio Casinovi: Effect of the switching order on power dissipation inswitched-capacitor circuits. 1389-1397
- Johannes Tausch, Junfeng Wang, Jacob K. White: Improved integral formulations for fast 3-D method-of-momentssolvers. 1398-1405
- Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong: Fast evaluation of sequence pair in block placement by longestcommon subsequence computation. 1406-1413
- Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha: Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. 1414-1425
- Ramesh C. Tekumalla, Premachandran R. Menon: Identification of primitive faults in combinational and sequentialcircuits. 1426-1442
- Yirng-An Chen, Randal E. Bryant: An efficient graph representation for arithmetic circuitverification. 1443-1454
- Jason Cong, Cheng-Kok Koh, Patrick H. Madden: Interconnect layout optimization under higher order RLC model forMCM designs. 1455-1463
- Jie Ding, Krishnendu Chakrabarty, Richard B. Fair: Scheduling of microfluidic operations for reconfigurabletwo-dimensional electrowetting arrays. 1463-1468
- Peeter Ellervee, Miguel Miranda, Francky Catthoor, Ahmed Hemani: System-level data-format exploration for dynamically allocated datastructures. 1469-1472
- Hüseyin Özkaramanli: A comparison of strong and weak distributed transverse couplingbetween VLSI interconnects. 1472-1478
- Wim F. J. Verhaegh, Emile H. L. Aarts, Paul C. N. van Gorp, Paul E. R. Lippens: Correction to "a two-stage solution approach to multidimensional periodic scheduling". 1479-1479
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