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@article{DBLP:journals/tcad/AcquavivaBR01,
author = {Andrea Acquaviva and
Luca Benini and
Bruno Ricc{\`{o}}},
title = {Software-controlled processor speed setting for low-power streamingmultimedia},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {11},
pages = {1283--1292},
year = {2001},
url = {https://doi.org/10.1109/43.959857},
doi = {10.1109/43.959857},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AcquavivaBR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Albrecht01,
author = {Christoph Albrecht},
title = {Global routing by new approximation algorithms for multicommodityflow},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {5},
pages = {622--632},
year = {2001},
url = {https://doi.org/10.1109/43.920691},
doi = {10.1109/43.920691},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Albrecht01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpertDFQ01,
author = {Charles J. Alpert and
Anirudh Devgan and
John P. Fishburn and
Stephen T. Quay},
title = {Interconnect synthesis without wire tapering},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {90--104},
year = {2001},
url = {https://doi.org/10.1109/43.905678},
doi = {10.1109/43.905678},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpertDFQ01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpertDK01,
author = {Charles J. Alpert and
Anirudh Devgan and
Chandramouli V. Kashyap},
title = {{RC} delay metrics for performance optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {5},
pages = {571--582},
year = {2001},
url = {https://doi.org/10.1109/43.920682},
doi = {10.1109/43.920682},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpertDK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpertGHNQS01,
author = {Charles J. Alpert and
Gopal Gandham and
Jiang Hu and
Jos{\'{e}} Luis Neves and
Stephen T. Quay and
Sachin S. Sapatnekar},
title = {Steiner tree optimization for buffers, blockages, and bays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {4},
pages = {556--562},
year = {2001},
url = {https://doi.org/10.1109/43.918213},
doi = {10.1109/43.918213},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpertGHNQS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AzizKSY01,
author = {Adnan Aziz and
James H. Kukula and
Thomas R. Shiple and
Jun Yuan},
title = {Efficient control state-space search},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {2},
pages = {332--336},
year = {2001},
url = {https://doi.org/10.1109/43.908475},
doi = {10.1109/43.908475},
timestamp = {Fri, 30 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/AzizKSY01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BaidasBW01,
author = {Zaher Abdulkarim Baidas and
Andrew D. Brown and
Alan Christopher Williams},
title = {Floating-point behavioral synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {7},
pages = {828--839},
year = {2001},
url = {https://doi.org/10.1109/43.931000},
doi = {10.1109/43.931000},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BaidasBW01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BayraktarogluO01,
author = {Ismet Bayraktaroglu and
Alex Orailoglu},
title = {Concurrent test for digital linear systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {9},
pages = {1132--1142},
year = {2001},
url = {https://doi.org/10.1109/43.945308},
doi = {10.1109/43.945308},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BayraktarogluO01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BeattieKAP01,
author = {Michael W. Beattie and
Byron Krauter and
Lale Alatan and
Lawrence T. Pileggi},
title = {Equipotential shells for efficient inductance extraction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {70--79},
year = {2001},
url = {https://doi.org/10.1109/43.905676},
doi = {10.1109/43.905676},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BeattieKAP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BelluominiMH01,
author = {Wendy Belluomini and
Chris J. Myers and
H. Peter Hofstee},
title = {Timed circuit verification using {TEL} structures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {129--146},
year = {2001},
url = {https://doi.org/10.1109/43.905681},
doi = {10.1109/43.905681},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BelluominiMH01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BeniniMLMOP01,
author = {Luca Benini and
Giovanni De Micheli and
Antonio Lioy and
Enrico Macii and
Giuseppe Odasso and
Massimo Poncino},
title = {Synthesis of power-managed sequential components based oncomputational
kernel extraction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {9},
pages = {1118--1131},
year = {2001},
url = {https://doi.org/10.1109/43.945307},
doi = {10.1109/43.945307},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BeniniMLMOP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BhattacharyaM01,
author = {Mayukh Bhattacharya and
Pinaki Mazumder},
title = {Augmentation of {SPICE} for simulation of circuits containingresonant
tunneling diodes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {39--50},
year = {2001},
url = {https://doi.org/10.1109/43.905673},
doi = {10.1109/43.905673},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BhattacharyaM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BrambillaM01,
author = {Angelo Brambilla and
Paolo Maffezzoni},
title = {Statistical method for the analysis of interconnects delay insubmicrometer
layouts},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {8},
pages = {957--966},
year = {2001},
url = {https://doi.org/10.1109/43.936377},
doi = {10.1109/43.936377},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BrambillaM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CarloniMS01,
author = {Luca P. Carloni and
Kenneth L. McMillan and
Alberto L. Sangiovanni{-}Vincentelli},
title = {Theory of latency-insensitive design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {9},
pages = {1059--1076},
year = {2001},
url = {https://doi.org/10.1109/43.945302},
doi = {10.1109/43.945302},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CarloniMS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Casinovi01,
author = {Giorgio Casinovi},
title = {Effect of the switching order on power dissipation inswitched-capacitor
circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {12},
pages = {1389--1397},
year = {2001},
url = {https://doi.org/10.1109/43.969432},
doi = {10.1109/43.969432},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Casinovi01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChandraC01,
author = {Anshuman Chandra and
Krishnendu Chakrabarty},
title = {System-on-a-chip test-data compression and decompressionarchitectures
based on Golomb codes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {3},
pages = {355--368},
year = {2001},
url = {https://doi.org/10.1109/43.913754},
doi = {10.1109/43.913754},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChandraC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangC01,
author = {Chin{-}Chih Chang and
Jason Cong},
title = {Pseudopin assignment with crosstalk noise control},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {5},
pages = {598--611},
year = {2001},
url = {https://doi.org/10.1109/43.920686},
doi = {10.1109/43.920686},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangCJLW01,
author = {Shih{-}Chieh Chang and
Ching{-}Hwa Cheng and
Wen{-}Ben Jone and
Shin{-}De Lee and
Jinn{-}Shyan Wang},
title = {Charge-sharing alleviation and detection for {CMOS} domino circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {2},
pages = {266--280},
year = {2001},
url = {https://doi.org/10.1109/43.908469},
doi = {10.1109/43.908469},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangCJLW01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangLW01,
author = {Yao{-}Wen Chang and
Jai{-}Ming Lin and
Martin D. F. Wong},
title = {Matching-based algorithm for {FPGA} channel segmentation design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {6},
pages = {784--791},
year = {2001},
url = {https://doi.org/10.1109/43.924831},
doi = {10.1109/43.924831},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangLW01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangR01,
author = {Shih{-}Chieh Chang and
Jiann{-}Chyi Rau},
title = {A timing-driven pseudoexhaustive testing for {VLSI} circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {147--158},
year = {2001},
url = {https://doi.org/10.1109/43.905682},
doi = {10.1109/43.905682},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangW01,
author = {Shih{-}Chieh Chang and
Zhong{-}Zhen Wu},
title = {Theorems and extensions of single wire replacement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {9},
pages = {1159--1164},
year = {2001},
url = {https://doi.org/10.1109/43.945310},
doi = {10.1109/43.945310},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangW01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenB01,
author = {Yirng{-}An Chen and
Randal E. Bryant},
title = {An efficient graph representation for arithmetic circuitverification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {12},
pages = {1443--1454},
year = {2001},
url = {https://doi.org/10.1109/43.969437},
doi = {10.1109/43.969437},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenD01,
author = {Li Chen and
Sujit Dey},
title = {Software-based self-testing methodology for processor cores},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {3},
pages = {369--380},
year = {2001},
url = {https://doi.org/10.1109/43.913755},
doi = {10.1109/43.913755},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenM01,
author = {Lauren Hui Chen and
Malgorzata Marek{-}Sadowska},
title = {Aggressor alignment for worst-case crosstalk noise},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {5},
pages = {612--621},
year = {2001},
url = {https://doi.org/10.1109/43.920689},
doi = {10.1109/43.920689},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongFK01,
author = {Jason Cong and
Jie Fang and
Kei{-}Yong Khoo},
title = {DUNE-a multilayer gridless routing system},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {5},
pages = {633--647},
year = {2001},
url = {https://doi.org/10.1109/43.920694},
doi = {10.1109/43.920694},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongFK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongH01,
author = {Jason Cong and
Yean{-}Yow Hwang},
title = {Boolean matching for LUT-based logic blocks with applications toarchitecture
evaluation and technology mapping},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {9},
pages = {1077--1090},
year = {2001},
url = {https://doi.org/10.1109/43.945303},
doi = {10.1109/43.945303},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongH01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongHKP01,
author = {Jason Cong and
Lei He and
Cheng{-}Kok Koh and
David Zhigang Pan},
title = {Interconnect sizing and spacing with consideration of couplingcapacitance},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {9},
pages = {1164--1169},
year = {2001},
url = {https://doi.org/10.1109/43.945311},
doi = {10.1109/43.945311},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongHKP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongKM01,
author = {Jason Cong and
Cheng{-}Kok Koh and
Patrick H. Madden},
title = {Interconnect layout optimization under higher order {RLC} model forMCM
designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {12},
pages = {1455--1463},
year = {2001},
url = {https://doi.org/10.1109/43.969438},
doi = {10.1109/43.969438},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongKM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CongP01,
author = {Jason Cong and
David Zhigang Pan},
title = {Interconnect performance estimation models for design planning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {6},
pages = {739--752},
year = {2001},
url = {https://doi.org/10.1109/43.924827},
doi = {10.1109/43.924827},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CongP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CordoneFSC01,
author = {Roberto Cordone and
Fabrizio Ferrandi and
Donatella Sciuto and
Roberto Wolfler Calvo},
title = {An efficient heuristic approach to solve the unate covering problem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {12},
pages = {1377--1388},
year = {2001},
url = {https://doi.org/10.1109/43.969431},
doi = {10.1109/43.969431},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CordoneFSC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DingCF01,
author = {Jie Ding and
Krishnendu Chakrabarty and
Richard B. Fair},
title = {Scheduling of microfluidic operations for reconfigurabletwo-dimensional
electrowetting arrays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {12},
pages = {1463--1468},
year = {2001},
url = {https://doi.org/10.1109/43.969439},
doi = {10.1109/43.969439},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/DingCF01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DrechslerGS01,
author = {Rolf Drechsler and
Wolfgang G{\"{u}}nther and
Fabio Somenzi},
title = {Using lower bounds during dynamic {BDD} minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {51--57},
year = {2001},
url = {https://doi.org/10.1109/43.905674},
doi = {10.1109/43.905674},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DrechslerGS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EllerveeMCH01,
author = {Peeter Ellervee and
Miguel Miranda and
Francky Catthoor and
Ahmed Hemani},
title = {System-level data-format exploration for dynamically allocated datastructures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {12},
pages = {1469--1472},
year = {2001},
url = {https://doi.org/10.1109/43.969440},
doi = {10.1109/43.969440},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/EllerveeMCH01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FallahDK01,
author = {Farzan Fallah and
Srinivas Devadas and
Kurt Keutzer},
title = {Functional vector generation for {HDL} models using linearprogramming
and Boolean satisfiability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {8},
pages = {994--1002},
year = {2001},
url = {https://doi.org/10.1109/43.936380},
doi = {10.1109/43.936380},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FallahDK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FallahDK01a,
author = {Farzan Fallah and
Srinivas Devadas and
Kurt Keutzer},
title = {OCCOM-efficient computation of observability-based code coveragemetrics
for functional verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {8},
pages = {1003--1015},
year = {2001},
url = {https://doi.org/10.1109/43.936381},
doi = {10.1109/43.936381},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FallahDK01a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FarrahiCSTS01,
author = {Amir H. Farrahi and
Chunhong Chen and
Ankur Srivastava and
Gustavo E. T{\'{e}}llez and
Majid Sarrafzadeh},
title = {Activity-driven clock design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {6},
pages = {705--714},
year = {2001},
url = {https://doi.org/10.1109/43.924824},
doi = {10.1109/43.924824},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/FarrahiCSTS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GauthierYJ01,
author = {Lovic Gauthier and
Sungjoo Yoo and
Ahmed Amine Jerraya},
title = {Automatic generation and targeting of application-specificoperating
systems and embedded systems software},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {11},
pages = {1293--1301},
year = {2001},
url = {https://doi.org/10.1109/43.959858},
doi = {10.1109/43.959858},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GauthierYJ01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GhoshF01,
author = {Indradeep Ghosh and
Masahiro Fujita},
title = {Automatic test pattern generation for functional register-transferlevel
circuits using assignment decision diagrams},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {3},
pages = {402--415},
year = {2001},
url = {https://doi.org/10.1109/43.913758},
doi = {10.1109/43.913758},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/GhoshF01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuoTCY01,
author = {Pei{-}Ning Guo and
Toshihiko Takahashi and
Chung{-}Kuan Cheng and
Takeshi Yoshimura},
title = {Floorplanning using a tree representation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {2},
pages = {281--289},
year = {2001},
url = {https://doi.org/10.1109/43.908471},
doi = {10.1109/43.908471},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuoTCY01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HafedOR01,
author = {Mohamed Hafed and
Mourad Oulmane and
Nicholas C. Rumin},
title = {Delay and current estimation in a {CMOS} inverter with an {RC} load},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {80--89},
year = {2001},
url = {https://doi.org/10.1109/43.905677},
doi = {10.1109/43.905677},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HafedOR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HershensonBL01,
author = {Maria del Mar Hershenson and
Stephen P. Boyd and
Thomas H. Lee},
title = {Optimal design of a {CMOS} op-amp via geometric programming},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {1--21},
year = {2001},
url = {https://doi.org/10.1109/43.905671},
doi = {10.1109/43.905671},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HershensonBL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HoffmannKNBSWWM01,
author = {Andreas Hoffmann and
Tim Kogel and
Achim Nohl and
Gunnar Braun and
Oliver Schliebusch and
Oliver Wahlen and
Andreas Wieferink and
Heinrich Meyr},
title = {A novel methodology for the design of application-specificinstruction-set
processors (ASIPs) using a machine description language},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {11},
pages = {1338--1354},
year = {2001},
url = {https://doi.org/10.1109/43.959863},
doi = {10.1109/43.959863},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HoffmannKNBSWWM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsiehBLS01,
author = {Harry Hsieh and
Felice Balarin and
Luciano Lavagno and
Alberto L. Sangiovanni{-}Vincentelli},
title = {Synchronous approach to the functional equivalence of embeddedsystem
implementations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {8},
pages = {1016--1033},
year = {2001},
url = {https://doi.org/10.1109/43.936382},
doi = {10.1109/43.936382},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsiehBLS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuanC01,
author = {Chung{-}Yang Huang and
Kwang{-}Ting Cheng},
title = {Using word-level {ATPG} and modular arithmetic constraint-solvingtechniques
for assertion property checking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {3},
pages = {381--391},
year = {2001},
url = {https://doi.org/10.1109/43.913756},
doi = {10.1109/43.913756},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HuanC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangL01,
author = {Tsung{-}Chu Huang and
Kuen{-}Jong Lee},
title = {Reduction of power consumption in scan-based circuits during testapplication
by an input control technique},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {7},
pages = {911--917},
year = {2001},
url = {https://doi.org/10.1109/43.931040},
doi = {10.1109/43.931040},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IvanovRRAB01,
author = {Andr{\'{e}} Ivanov and
Sumbal Rafiq and
Michel Renovell and
Florence Aza{\"{\i}}s and
Yves Bertrand},
title = {On the detectability of {CMOS} floating gate transistor faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {116--128},
year = {2001},
url = {https://doi.org/10.1109/43.905680},
doi = {10.1109/43.905680},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IvanovRRAB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngLMMMPTWW01,
author = {Andrew B. Kahng and
John C. Lach and
William H. Mangione{-}Smith and
Stefanus Mantik and
Igor L. Markov and
Miodrag Potkonjak and
Paul Tucker and
Huijuan Wang and
Gregory Wolfe},
title = {Constraint-based watermarking techniques for design {IP} protection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {10},
pages = {1236--1252},
year = {2001},
url = {https://doi.org/10.1109/43.952740},
doi = {10.1109/43.952740},
timestamp = {Fri, 20 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngLMMMPTWW01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngMS01,
author = {Andrew B. Kahng and
Stefanus Mantik and
Dirk Stroobandt},
title = {Toward accurate models of achievable routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {5},
pages = {648--659},
year = {2001},
url = {https://doi.org/10.1109/43.920697},
doi = {10.1109/43.920697},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngMS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Karri01,
author = {Ramesh Karri},
title = {Guest editor's introduction to special section on high-level design
validation and test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {3},
pages = {353--354},
year = {2001},
url = {https://doi.org/10.1109/TCAD.2001.913753},
doi = {10.1109/TCAD.2001.913753},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Karri01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KayR01,
author = {Rony Kay and
Rob A. Rutenbar},
title = {Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer
assignment with an efficient integer programming solution},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {5},
pages = {672--679},
year = {2001},
url = {https://doi.org/10.1109/43.920702},
doi = {10.1109/43.920702},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KayR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KhouriJ01,
author = {Kamal S. Khouri and
Niraj K. Jha},
title = {Clock selection for performance optimization of control-flowintensive
behaviors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {158--165},
year = {2001},
url = {https://doi.org/10.1109/43.905683},
doi = {10.1109/43.905683},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KhouriJ01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimH01,
author = {HyungWon Kim and
John P. Hayes},
title = {Realization-independent {ATPG} for designs with unimplemented blocks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {2},
pages = {290--306},
year = {2001},
url = {https://doi.org/10.1109/43.908472},
doi = {10.1109/43.908472},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimH01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimK01,
author = {Ki{-}Wook Kim and
Sung{-}Mo Kang},
title = {Crosstalk noise minimization in domino logic design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {9},
pages = {1091--1100},
year = {2001},
url = {https://doi.org/10.1109/43.945305},
doi = {10.1109/43.945305},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KoushanfarKHPP01,
author = {Farinaz Koushanfar and
Darko Kirovski and
Inki Hong and
Miodrag Potkonjak and
Marios C. Papaefthymiou},
title = {Symbolic debugging of embedded hardware and software},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {3},
pages = {392--401},
year = {2001},
url = {https://doi.org/10.1109/43.913757},
doi = {10.1109/43.913757},
timestamp = {Fri, 04 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KoushanfarKHPP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KrsticJC01,
author = {Angela Krstic and
Yi{-}Min Jiang and
Kwang{-}Ting Cheng},
title = {Pattern generation for delay testing and dynamic timing analysisconsidering
power-supply noise effects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {3},
pages = {416--425},
year = {2001},
url = {https://doi.org/10.1109/43.913759},
doi = {10.1109/43.913759},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KrsticJC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KuhlmannS01,
author = {Martin Kuhlmann and
Sachin S. Sapatnekar},
title = {Exact and efficient crosstalk estimation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {7},
pages = {858--866},
year = {2001},
url = {https://doi.org/10.1109/43.931008},
doi = {10.1109/43.931008},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KuhlmannS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KumS01,
author = {Ki{-}Il Kum and
Wonyong Sung},
title = {Combined word-length optimization and high-level synthesis ofdigital
signal processing systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {8},
pages = {921--930},
year = {2001},
url = {https://doi.org/10.1109/43.936374},
doi = {10.1109/43.936374},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KumS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LachMP01,
author = {John C. Lach and
William H. Mangione{-}Smith and
Miodrag Potkonjak},
title = {Fingerprinting techniques for field-programmable gate arrayintellectual
property protection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {10},
pages = {1253--1261},
year = {2001},
url = {https://doi.org/10.1109/43.952741},
doi = {10.1109/43.952741},
timestamp = {Fri, 20 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LachMP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LahiriRD01,
author = {Kanishka Lahiri and
Anand Raghunathan and
Sujit Dey},
title = {System-level performance analysis for designing on-chipcommunication
architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {6},
pages = {768--783},
year = {2001},
url = {https://doi.org/10.1109/43.924830},
doi = {10.1109/43.924830},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LahiriRD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeKPM01,
author = {Kyu{-}Il Lee and
Jinsoo Kim and
Young June Park and
Hong{-}Shick Min},
title = {Simple frequency-domain analysis of MOSFET-includingnonquasi-static
effect},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {7},
pages = {867--876},
year = {2001},
url = {https://doi.org/10.1109/43.931011},
doi = {10.1109/43.931011},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeKPM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaLTYL01,
author = {Yutao Ma and
Litian Liu and
Lilin Tian and
Zhiping Yu and
Zhijian Li},
title = {Analytical charge-control and {I-V} model for submicrometer anddeep-submicrometer
MOSFETs fully comprising quantum mechanical effects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {4},
pages = {495--502},
year = {2001},
url = {https://doi.org/10.1109/43.918208},
doi = {10.1109/43.918208},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaLTYL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MahlkeRSSS01,
author = {Scott A. Mahlke and
Rajiv A. Ravindran and
Michael S. Schlansker and
Robert Schreiber and
Timothy Sherwood},
title = {Bitwidth cognizant architecture synthesis of custom hardwareaccelerators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {11},
pages = {1355--1371},
year = {2001},
url = {https://doi.org/10.1109/43.959864},
doi = {10.1109/43.959864},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MahlkeRSSS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MandalV01,
author = {Pradip Mandal and
V. Visvanathan},
title = {{CMOS} op-amp sizing using a geometric programming formulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {22--38},
year = {2001},
url = {https://doi.org/10.1109/43.905672},
doi = {10.1109/43.905672},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MandalV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Marwedel01,
author = {Peter Marwedel},
title = {Guest editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {11},
pages = {1281--1282},
year = {2001},
url = {https://doi.org/10.1109/TCAD.2001.959856},
doi = {10.1109/TCAD.2001.959856},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Marwedel01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/McDonaldB01,
author = {Clayton B. McDonald and
Randal E. Bryant},
title = {{CMOS} circuit verification with symbolic switch-level timingsimulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {3},
pages = {458--474},
year = {2001},
url = {https://doi.org/10.1109/43.913762},
doi = {10.1109/43.913762},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/McDonaldB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MeurisSM01,
author = {Peter Meuris and
Wim Schoenmaker and
Wim Magnus},
title = {Strategy for electromagnetic interconnect modeling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {6},
pages = {753--762},
year = {2001},
url = {https://doi.org/10.1109/43.924828},
doi = {10.1109/43.924828},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MeurisSM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MoC01,
author = {Yu{-}Yen Mo and
Chris C. N. Chu},
title = {Hybrid dynamic/quadratic programming algorithm for interconnecttree
optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {5},
pages = {680--686},
year = {2001},
url = {https://doi.org/10.1109/43.920705},
doi = {10.1109/43.920705},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MoC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MurthyB01,
author = {Praveen K. Murthy and
Shuvra S. Bhattacharyya},
title = {Shared buffer implementations of signal processing systems usinglifetime
analysis techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {2},
pages = {177--198},
year = {2001},
url = {https://doi.org/10.1109/43.908427},
doi = {10.1109/43.908427},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MurthyB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OhP01,
author = {Jaewon Oh and
Massoud Pedram},
title = {Gated clock routing for low-power microprocessor design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {6},
pages = {715--722},
year = {2001},
url = {https://doi.org/10.1109/43.924825},
doi = {10.1109/43.924825},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OhP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Oliveira01,
author = {Arlindo L. Oliveira},
title = {Techniques for the creation of digital watermarks in sequentialcircuit
designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {9},
pages = {1101--1117},
year = {2001},
url = {https://doi.org/10.1109/43.945306},
doi = {10.1109/43.945306},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Oliveira01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Ozkaramanli01,
author = {H{\"{u}}seyin {\"{O}}zkaramanli},
title = {A comparison of strong and weak distributed transverse couplingbetween
{VLSI} interconnects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {12},
pages = {1472--1478},
year = {2001},
url = {https://doi.org/10.1109/43.969441},
doi = {10.1109/43.969441},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Ozkaramanli01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PantHGC01,
author = {Pankaj Pant and
Yuan{-}Chieh Hsu and
Sandeep K. Gupta and
Abhijit Chatterjee},
title = {Path delay fault diagnosis in combinational circuits with implicitfault
enumeration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {10},
pages = {1226--1235},
year = {2001},
url = {https://doi.org/10.1109/43.952739},
doi = {10.1109/43.952739},
timestamp = {Fri, 22 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PantHGC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Papadopoulou01,
author = {Evanthia Papadopoulou},
title = {Critical area computation for missing material defects in VLSIcircuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {5},
pages = {583--597},
year = {2001},
url = {https://doi.org/10.1109/43.920683},
doi = {10.1109/43.920683},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Papadopoulou01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ParkC01,
author = {Sanghun Park and
Kiyoung Choi},
title = {Performance-driven high-level synthesis with bit-level chaining andclock
selection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {2},
pages = {199--212},
year = {2001},
url = {https://doi.org/10.1109/43.908436},
doi = {10.1109/43.908436},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ParkC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PendurkarCZ01,
author = {Rajesh Pendurkar and
Abhijit Chatterjee and
Yervant Zorian},
title = {Switching activity generation with automated {BIST} synthesis forperformance
testing of interconnects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {9},
pages = {1143--1158},
year = {2001},
url = {https://doi.org/10.1109/43.945309},
doi = {10.1109/43.945309},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PendurkarCZ01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PetrovO01,
author = {Peter Petrov and
Alex Orailoglu},
title = {Performance and power effectiveness in embedded processors customizable
partitioned caches},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {11},
pages = {1309--1318},
year = {2001},
url = {https://doi.org/10.1109/43.959860},
doi = {10.1109/43.959860},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PetrovO01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PlasDLLVGSVL01,
author = {Geert Van der Plas and
Geert Debyser and
Francky Leyn and
Koen Lampaert and
Jan Vandenbussche and
Georges G. E. Gielen and
Willy M. C. Sansen and
Petar Veselinovic and
Domine Leenaerts},
title = {{AMGIE-A} synthesis environment for {CMOS} analog integrated circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {9},
pages = {1037--1058},
year = {2001},
url = {https://doi.org/10.1109/43.945301},
doi = {10.1109/43.945301},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PlasDLLVGSVL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR01,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Vector replacement to improve static-test compaction forsynchronous
sequential circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {2},
pages = {336--342},
year = {2001},
url = {https://doi.org/10.1109/43.908476},
doi = {10.1109/43.908476},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR01a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On diagnosis and diagnostic test generation for pattern-dependenttransition
faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {6},
pages = {791--800},
year = {2001},
url = {https://doi.org/10.1109/43.924832},
doi = {10.1109/43.924832},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR01a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR01b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Forward-looking fault simulation for improved static compaction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {10},
pages = {1262--1265},
year = {2001},
url = {https://doi.org/10.1109/43.952743},
doi = {10.1109/43.952743},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR01b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzZ01,
author = {Irith Pomeranz and
Y. Zonan},
title = {Testing of scan circuits containing nonisolated random-logic legacycores},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {8},
pages = {980--993},
year = {2001},
url = {https://doi.org/10.1109/43.936379},
doi = {10.1109/43.936379},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzZ01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/QiuQP01,
author = {Qinru Qiu and
Qing Qu and
Massoud Pedram},
title = {Stochastic modeling of a power-managed system-construction andoptimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {10},
pages = {1200--1217},
year = {2001},
url = {https://doi.org/10.1109/43.952737},
doi = {10.1109/43.952737},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/QiuQP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RajagopalanRMRAT01,
author = {Subramanian Rajagopalan and
Sreeranga P. Rajan and
Sharad Malik and
Sandro Rigo and
Guido Araujo and
Koichiro Takayama},
title = {A retargetable {VLIW} compiler framework for DSPs withinstruction-level
parallelism},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {11},
pages = {1319--1328},
year = {2001},
url = {https://doi.org/10.1109/43.959861},
doi = {10.1109/43.959861},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RajagopalanRMRAT01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RaviGBJ01,
author = {Srivaths Ravi and
Indradeep Ghosh and
Vamsi Boppana and
Niraj K. Jha},
title = {Fault-diagnosis-based technique for establishing {RTL} and gate-levelcorrespondences},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {12},
pages = {1414--1425},
year = {2001},
url = {https://doi.org/10.1109/43.969435},
doi = {10.1109/43.969435},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/RaviGBJ01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RaviLJ01,
author = {Srivaths Ravi and
Ganesh Lakshminarayana and
Niraj K. Jha},
title = {Testing of core-based systems-on-a-chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {3},
pages = {426--439},
year = {2001},
url = {https://doi.org/10.1109/43.913760},
doi = {10.1109/43.913760},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RaviLJ01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ReleJPR01,
author = {Siddharth Rele and
Vipin Jain and
Santosh Pande and
J. Ramanujam},
title = {Compact and efficient code generation through program restructuringon
limited memory embedded DSPs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {4},
pages = {477--494},
year = {2001},
url = {https://doi.org/10.1109/43.918207},
doi = {10.1109/43.918207},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ReleJPR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RestleRWP01,
author = {Phillip J. Restle and
Albert E. Ruehli and
Steven G. Walker and
George Papadopoulos},
title = {Full-wave {PEEC} time-domain method for the modeling of on-chipinterconnects},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {7},
pages = {877--886},
year = {2001},
url = {https://doi.org/10.1109/43.931029},
doi = {10.1109/43.931029},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/RestleRWP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RhodesW01,
author = {David L. Rhodes and
Wayne H. Wolf},
title = {RAGS-real-analysis ALAP-guided synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {8},
pages = {931--941},
year = {2001},
url = {https://doi.org/10.1109/43.936375},
doi = {10.1109/43.936375},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RhodesW01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RuanSLT01,
author = {Shanq{-}Jang Ruan and
Rung{-}Ji Shang and
Feipei Lai and
Kun{-}Lin Tsai},
title = {A bipartition-codec architecture to reduce power in pipelinedcircuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {2},
pages = {343--348},
year = {2001},
url = {https://doi.org/10.1109/43.908477},
doi = {10.1109/43.908477},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RuanSLT01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SaabHK01,
author = {Khaled Saab and
Naim Ben{-}Hamida and
Bozena Kaminska},
title = {Closing the gap between analog and digital testing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {2},
pages = {307--314},
year = {2001},
url = {https://doi.org/10.1109/43.908473},
doi = {10.1109/43.908473},
timestamp = {Thu, 22 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SaabHK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SarkarK01,
author = {Probir Sarkar and
Cheng{-}Kok Koh},
title = {Routability-driven repeater block planning for interconnect-centricfloorplanning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {5},
pages = {660--671},
year = {2001},
url = {https://doi.org/10.1109/43.920700},
doi = {10.1109/43.920700},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SarkarK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SaxenaL01,
author = {Prashant Saxena and
C. L. Liu},
title = {Optimization of the maximum delay of global interconnects duringlayer
assignment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {4},
pages = {503--515},
year = {2001},
url = {https://doi.org/10.1109/43.918209},
doi = {10.1109/43.918209},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SaxenaL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SemeriaM01,
author = {Luc S{\'{e}}m{\'{e}}ria and
Giovanni De Micheli},
title = {Resolution, optimization, and encoding of pointer variables for thebehavioral
synthesis from {C}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {2},
pages = {213--233},
year = {2001},
url = {https://doi.org/10.1109/43.908442},
doi = {10.1109/43.908442},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SemeriaM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShepardK01,
author = {Kenneth L. Shepard and
Dae{-}Jin Kim},
title = {Body-voltage estimation in digital {PD-SOI} circuits and itsapplication
to static timing analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {7},
pages = {888--901},
year = {2001},
url = {https://doi.org/10.1109/43.931033},
doi = {10.1109/43.931033},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShepardK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShiT01,
author = {C.{-}J. Richard Shi and
Sheldon X.{-}D. Tan},
title = {Compact representation and efficient generation of s-expandedsymbolic
network functions for computer-aided analog circuit design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {7},
pages = {813--827},
year = {2001},
url = {https://doi.org/10.1109/43.930996},
doi = {10.1109/43.930996},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShiT01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SimunicBGM01,
author = {Tajana Simunic and
Luca Benini and
Peter W. Glynn and
Giovanni De Micheli},
title = {Event-driven power management},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {7},
pages = {840--857},
year = {2001},
url = {https://doi.org/10.1109/43.931003},
doi = {10.1109/43.931003},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SimunicBGM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinghalPAB01,
author = {Vigyan Singhal and
Carl Pixley and
Adnan Aziz and
Robert K. Brayton},
title = {Theory of safe replacements for sequential circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {2},
pages = {249--265},
year = {2001},
url = {https://doi.org/10.1109/43.908455},
doi = {10.1109/43.908455},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinghalPAB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SivaramanS01,
author = {Mukund Sivaraman and
Andrzej J. Strojwas},
title = {Path delay fault diagnosis and coverage-a metric and an estimationtechnique},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {3},
pages = {440--457},
year = {2001},
url = {https://doi.org/10.1109/43.913761},
doi = {10.1109/43.913761},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SivaramanS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SmyWD01,
author = {Tom J. Smy and
David J. Walkey and
Steven K. Dew},
title = {A 3D thermal simulation tool for integrated devices-Atar},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {105--115},
year = {2001},
url = {https://doi.org/10.1109/43.905679},
doi = {10.1109/43.905679},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SmyWD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SrivastavaKS01,
author = {Ankur Srivastava and
Ryan Kastner and
Majid Sarrafzadeh},
title = {On the complexity of gate duplication},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {9},
pages = {1170--1176},
year = {2001},
url = {https://doi.org/10.1109/43.945312},
doi = {10.1109/43.945312},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SrivastavaKS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/StankovicS01,
author = {Radomir S. Stankovic and
Tsutomu Sasao},
title = {A discussion on the history of research in arithmetic andReed-Muller
expressions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {9},
pages = {1177--1179},
year = {2001},
url = {https://doi.org/10.1109/43.945313},
doi = {10.1109/43.945313},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/StankovicS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SuBNP01,
author = {Lixin Su and
Wray L. Buntine and
A. Richard Newton and
Bradley S. Peters},
title = {Learning as applied to stochastic optimization for standard-cellplacement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {4},
pages = {516--527},
year = {2001},
url = {https://doi.org/10.1109/43.918210},
doi = {10.1109/43.918210},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SuBNP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TangTW01,
author = {Xiaoping Tang and
Ruiqi Tian and
Martin D. F. Wong},
title = {Fast evaluation of sequence pair in block placement by longestcommon
subsequence computation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {12},
pages = {1406--1413},
year = {2001},
url = {https://doi.org/10.1109/43.969434},
doi = {10.1109/43.969434},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TangTW01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TauschWW01,
author = {Johannes Tausch and
Junfeng Wang and
Jacob K. White},
title = {Improved integral formulations for fast 3-D method-of-momentssolvers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {12},
pages = {1398--1405},
year = {2001},
url = {https://doi.org/10.1109/43.969433},
doi = {10.1109/43.969433},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TauschWW01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TekumallaM01,
author = {Ramesh C. Tekumalla and
Premachandran R. Menon},
title = {Identification of primitive faults in combinational and sequentialcircuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {12},
pages = {1426--1442},
year = {2001},
url = {https://doi.org/10.1109/43.969436},
doi = {10.1109/43.969436},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TekumallaM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TianWB01,
author = {Ruiqi Tian and
Martin D. F. Wong and
Robert Boone},
title = {Model-based dummy feature placement for oxide chemical-mechanicalpolishing
manufacturability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {7},
pages = {902--910},
year = {2001},
url = {https://doi.org/10.1109/43.931037},
doi = {10.1109/43.931037},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TianWB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ToubaM01,
author = {Nur A. Touba and
Edward J. McCluskey},
title = {Bit-fixing in pseudorandom sequences for scan {BIST}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {4},
pages = {545--555},
year = {2001},
url = {https://doi.org/10.1109/43.918212},
doi = {10.1109/43.918212},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ToubaM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TsengSS01,
author = {Hsiao{-}Ping Tseng and
Louis Scheffer and
Carl Sechen},
title = {Timing- and crosstalk-driven area routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {4},
pages = {528--544},
year = {2001},
url = {https://doi.org/10.1109/43.918211},
doi = {10.1109/43.918211},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TsengSS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VaishnavP01,
author = {Hirendu Vaishnav and
Massoud Pedram},
title = {Alphabetic trees-theory and applications in layout-driven logicsynthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {58--69},
year = {2001},
url = {https://doi.org/10.1109/43.905675},
doi = {10.1109/43.905675},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VaishnavP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VerhaeghAGL01,
author = {Wim F. J. Verhaegh and
Emile H. L. Aarts and
Paul C. N. van Gorp and
Paul E. R. Lippens},
title = {A two-stage solution approach to multidimensional periodicscheduling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {10},
pages = {1185--1199},
year = {2001},
url = {https://doi.org/10.1109/43.952736},
doi = {10.1109/43.952736},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VerhaeghAGL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VerhaeghAGL01a,
author = {Wim F. J. Verhaegh and
Emile H. L. Aarts and
Paul C. N. van Gorp and
Paul E. R. Lippens},
title = {Correction to "a two-stage solution approach to multidimensional periodic
scheduling"},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {12},
pages = {1479--1479},
year = {2001},
url = {https://doi.org/10.1109/TCAD.2001.969442},
doi = {10.1109/TCAD.2001.969442},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VerhaeghAGL01a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WagnerL01,
author = {Jens Wagner and
Rainer Leupers},
title = {C compiler design for a network processor},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {11},
pages = {1302--1308},
year = {2001},
url = {https://doi.org/10.1109/43.959859},
doi = {10.1109/43.959859},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WagnerL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangL01,
author = {Lih{-}Yang Wang and
Yen{-}Tai Lai},
title = {Graph-theory-based simplex algorithm for {VLSI} layout spacingproblems
with multiple variable constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {8},
pages = {967--979},
year = {2001},
url = {https://doi.org/10.1109/43.936378},
doi = {10.1109/43.936378},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WassalH01,
author = {Amr G. Wassal and
M. Anwar Hasan},
title = {Low-power system-level design of {VLSI} packet switching fabrics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {6},
pages = {723--738},
year = {2001},
url = {https://doi.org/10.1109/43.924826},
doi = {10.1109/43.924826},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WassalH01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WehmeyerJSMB01,
author = {Lars Wehmeyer and
Manoj Kumar Jain and
Stefan Steinke and
Peter Marwedel and
M. Balakrishnan},
title = {Analysis of the influence of register file size on energyconsumption,
code size, and execution time},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {11},
pages = {1329--1337},
year = {2001},
url = {https://doi.org/10.1109/43.959862},
doi = {10.1109/43.959862},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WehmeyerJSMB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WeinhardtL01,
author = {Markus Weinhardt and
Wayne Luk},
title = {Pipeline vectorization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {2},
pages = {234--248},
year = {2001},
url = {https://doi.org/10.1109/43.908452},
doi = {10.1109/43.908452},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WeinhardtL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WenL01,
author = {Yun{-}Che Wen and
Kuen{-}Jong Lee},
title = {Analysis and generation of control and observation structures foranalog
circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {165--171},
year = {2001},
url = {https://doi.org/10.1109/43.905684},
doi = {10.1109/43.905684},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WenL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuGLHC01,
author = {Zilu Wu and
Yumin Gao and
Jinsheng Luo and
Xun Hou and
Guofu Chen},
title = {Application of {BEM} to high-voltage junction termination},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {10},
pages = {1218--1225},
year = {2001},
url = {https://doi.org/10.1109/43.952738},
doi = {10.1109/43.952738},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuGLHC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuLC01,
author = {Guang{-}Ming Wu and
Jai{-}Ming Lin and
Yao{-}Wen Chang},
title = {Generic ILP-based approaches for time-multiplexed {FPGA} partitioning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {10},
pages = {1266--1274},
year = {2001},
url = {https://doi.org/10.1109/43.952745},
doi = {10.1109/43.952745},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuLC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuQP01,
author = {Qing Wu and
Qinru Qiu and
Massoud Pedram},
title = {Estimation of peak power dissipation in {VLSI} circuits using thelimiting
distributions of extreme order statistics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {8},
pages = {942--956},
year = {2001},
url = {https://doi.org/10.1109/43.936376},
doi = {10.1109/43.936376},
timestamp = {Tue, 12 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WuQP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YalcinMPBSH01,
author = {Hakan Yalcin and
Mohammad Mortazavi and
Robert Palermo and
Cyrus Bamji and
Karem A. Sakallah and
John P. Hayes},
title = {Fast and accurate timing characterization using functionalinformation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {2},
pages = {315--331},
year = {2001},
url = {https://doi.org/10.1109/43.908474},
doi = {10.1109/43.908474},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YalcinMPBSH01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YehKJ01,
author = {Yi{-}Jong Yeh and
Sy{-}Yen Kuo and
Jing{-}Yang Jou},
title = {Converter-free multiple-voltage scaling techniques for low-powerCMOS
digital design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {1},
pages = {172--176},
year = {2001},
url = {https://doi.org/10.1109/43.905685},
doi = {10.1109/43.905685},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YehKJ01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YoungCLW01,
author = {Evangeline F. Y. Young and
Chris C. N. Chu and
W. S. Luk and
Y. C. Wong},
title = {Handling soft modules in general nonslicing floorplan usingLagrangian
relaxation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {5},
pages = {687--692},
year = {2001},
url = {https://doi.org/10.1109/43.920707},
doi = {10.1109/43.920707},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YoungCLW01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YoungWY01,
author = {Evangeline F. Y. Young and
Martin D. F. Wong and
Hannah Honghua Yang},
title = {On extending slicing floorplan to handle L/T-shaped modules andabutment
constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {6},
pages = {800--807},
year = {2001},
url = {https://doi.org/10.1109/43.924833},
doi = {10.1109/43.924833},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YoungWY01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhouA01,
author = {Hai Zhou and
Adnan Aziz},
title = {Buffer minimization in pass transistor logic},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {5},
pages = {693--697},
year = {2001},
url = {https://doi.org/10.1109/43.920711},
doi = {10.1109/43.920711},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhouA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhouCF01,
author = {Junlin Zhou and
Mengzhang Cheng and
Leonard Forbes},
title = {{SPICE} models for flicker noise in p-MOSFETs in the saturationregion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {6},
pages = {763--767},
year = {2001},
url = {https://doi.org/10.1109/43.924829},
doi = {10.1109/43.924829},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhouCF01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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