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ORCIDGanesh Lakshminarayana
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2000 – 2009
- 2006
[j21]Kanishka Lahiri, Anand Raghunathan
, Ganesh Lakshminarayana:
The LOTTERYBUS on-chip communication architecture. IEEE Trans. Very Large Scale Integr. Syst. 14(6): 596-608 (2006)- 2005
- [j20]Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input space-adaptive optimization for embedded-software synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1677-1693 (2005) - [j19]Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
Memory binding for performance optimization of control-flow intensive behavioral descriptions. IEEE Trans. Very Large Scale Integr. Syst. 13(5): 513-524 (2005) - 2004
- [j18]Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey:
Common-case computation: a high-level energy and performance optimization technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 33-49 (2004) - [j17]Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey:
Design of high-performance system-on-chips using communication architecture tuners. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 620-636 (2004) - [j16]Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input space adaptive design: a high-level methodology for optimizing energy and performance. IEEE Trans. Very Large Scale Integr. Syst. 12(6): 590-602 (2004) - 2003
- [j15]Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Analysis of power dissipation in embedded systems using real-time operating systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 615-627 (2003) - 2002
- [j14]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
High-level test compaction techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7): 827-841 (2002) - [j13]Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
High-level energy macromodeling of embedded software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9): 1037-1050 (2002) - [c27]Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana:
Optimizing public-key encryption for wireless clients. ICC 2002: 1050-1056 - [c26]Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input Space Adaptive Embedded Software Synthesis. ASP-DAC/VLSI Design 2002: 711-718 - 2001
- [j12]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
Testing of core-based systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3): 426-439 (2001) - [j11]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
TAO: regular expression-based register-transfer level testability analysis and optimization. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 824-832 (2001) - [c25]Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana:
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. DAC 2001: 15-20 - [c24]Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
High-level Software Energy Macro-modeling. DAC 2001: 605-610 - [c23]Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. DAC 2001: 738-743 - [c22]Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana:
Transient Power Management Through High Level Synthesis. ICCAD 2001: 545-552 - [c21]Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar:
Accurate Power Macro-modeling Techniques for Complex RTL Circuits. VLSI Design 2001: 235-241 - 2000
- [j10]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis. IEEE Trans. Computers 49(9): 865-885 (2000) - [j9]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(3): 308-324 (2000) - [j8]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 894-906 (2000) - [j7]Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana:
Integrating variable-latency components into high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(10): 1105-1117 (2000) - [c20]Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Power analysis of embedded operating systems. DAC 2000: 312-315 - [c19]Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey:
Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. DAC 2000: 513-518 - [c18]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
: Reducing test application time in high-level test generation. ITC 2000: 829-838 - [c17]Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana:
High-Level Synthesis with Variable-Latency Components. VLSI Design 2000: 220-227
1990 – 1999
- 1999
- [j6]Ganesh Lakshminarayana, Niraj K. Jha:
High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3): 265-281 (1999) - [j5]Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha:
Wavesched: a novel scheduling technique for control-flow intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(5): 505-523 (1999) - [j4]Ganesh Lakshminarayana, Niraj K. Jha:
FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1577-1594 (1999) - [j3]Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
High-level synthesis of low-power control-flow intensive circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12): 1715-1729 (1999) - [j2]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
Power management in high-level synthesis. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 7-15 (1999) - [j1]Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha:
COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 92-104 (1999) - [c16]Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey:
Common-Case Computation: A High-Level Technique for Power and Performance Optimization. DAC 1999: 56-61 - [c15]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
A framework for testing core-based systems-on-a-chip. ICCAD 1999: 385-390 - [c14]Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
Memory binding for performance optimization of control-flow intensive behaviors. ICCAD 1999: 482-488 - [c13]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. VTS 1999: 398-406 - 1998
- [c12]Ganesh Lakshminarayana, Niraj K. Jha:
FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions. DAC 1998: 102-107 - [c11]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. DAC 1998: 108-113 - [c10]Ganesh Lakshminarayana, Niraj K. Jha:
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions. DAC 1998: 439-444 - [c9]Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits. DATE 1998: 848-854 - [c8]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. ICCAD 1998: 577-584 - [c7]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
Transforming control-flow intensive designs to facilitate power management. ICCAD 1998: 657-664 - [c6]Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
Fast high-level power estimation for control-flow intensive design. ISLPED 1998: 299-304 - [c5]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
TAO: regular expression based high-level testability analysis and optimization. ITC 1998: 331-340 - [c4]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
A Power Management Methodology for High-Level Synthesis. VLSI Design 1998: 24-19 - 1997
- [c3]Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha:
COSYN: Hardware-Software Co-Synthesis of Embedded Systems. DAC 1997: 703-708 - [c2]Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha:
Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions. ICCAD 1997: 244-250 - 1996
- [c1]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis. FTCS 1996: 336-345
Coauthor Index
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