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ORCIDIEEE Journal of Solid-State Circuits, Volume 35
Volume 35, Number 1, January 2000
- Raúl Andrés Bianchi, Jean-Michel Karam, Bernard Courtois:
Analog ALC crystal oscillators for high-temperature applications. 2-14 - Hooman Darabi, Asad A. Abidi:
Noise in RF-CMOS mixers: a simple physical model. 15-25 - Gabriel A. Rincón-Mora:
Active capacitor multiplier in Miller-compensated circuits. 26-32 - J. Francisco Duque-Carrillo
, José L. Ausín, Guido Torelli, José M. Valverde, Miguel Angel Domínguez:
1-V rail-to-rail operational amplifiers in standard CMOS technology. 33-44 - Chenghung James Pan:
A stereo audio chip using approximate processing for decimation and interpolation filters. 45-55 - Pierte Roo, Richard R. Spencer, Paul J. Hurst:
A CMOS analog timing recovery circuit for PRML detectors. 56-65 - Naoki Harada, Akira Watanabe, Yuji Awano, Kohki Hikosaka, Naoki Yokoyama:
A multigigahertz Josephson-semiconductor interface circuit using 77-K differential monolithic HEMT amplifier and 4.2-K JJ high-voltage driver for superconductor-semiconductor electronic hybrid systems. 66-73 - Jong-Seok Kim, Deog-Kyoon Jeong, Gyudong Kim:
A multi-level multi-phase charge-recycling method for low-power AMLCD column drivers. 74-84 - Richard C. Jaeger, Jeffrey C. Suhling, Ramanathan Ramani, Arthur T. Bradley, Jianping Xu:
CMOS stress sensors on [100] silicon. 85-95 - Carlo Samori, Andrea L. Lacaita, Alfio Zanchi, Salvatore Levantino, Giovanni Calí:
Phase noise degradation at high oscillation amplitudes in LC-tuned VCO's. 96-99 - Chih-Ming Hung, Kenneth K. O:
A packaged 1.1-GHz CMOS VCO with phase noise of -126 dBc/Hz at a 600-kHz offset. 100-103 - Paolo Orsatti, Francesco Piazza, Qiuting Huang:
A 71-MHz CMOS IF-baseband strip for GSM. 104-108 - Liang Dai, Ramesh Harjani:
CMOS switched-op-amp-based sample-and-hold circuit. 109-113 - Chua-Chin Wang, Chi-Feng Wu, Rain-Ted Hwang, Chia-Hsiung Kao:
Single-ended SRAM with high test coverage and short test time. 114-118 - Jinn-Shyan Wang, Wayne Tseng, Hung-Yu Li:
Low-power embedded SRAM with the current-mode write technique. 119-124 - Wei Hwang, Rajiv V. Joshi, George Gristede:
A scannable pulse-to-static conversion register array for self-timed circuits. 125-128 - Kush Gulati, Hae-Seung Lee:
Corrections to "a high-swing CMOS telescopic operational amplifier". 129
Volume 35, Number 2, February 2000
- Fenghao Mu, Christer Svensson:
Pulsewidth control loop in high-speed CMOS clock buffers. 134-141 - Peter Hazucha, Christer Svensson:
Optimized test circuits for SER characterization of a manufacturing process. 142-148 - Yasuhiro Takai, Mamoru Fujita, Kyoichi Nagata, Satoshi Isa, Shigeyuki Nakazawa, Atsunori Hirobe, Hiroaki Ohkubo, Masato Sakao, Shinichi Horiba, Tadashi Fukase, Yoshihiro Takaishi, Makoto Matsuo, Masahiro Komuro, Tetsuya Uchida, Takashi Sakoh, Kanta Saino, Shirou Uchiyama, Yuichi Takada, Junichi Sekine, Nobuko Nakanishi, Takeshi Oikawa, Masahiko Igeta, Hiroyoshi Tanabe, Hidenobu Miyamoto, Takeo Hashimoto, Hiromu Yamaguchi, Kuniaki Koyama, Yasuo Kobayashi, Takashi Okuda:
A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme. 149-162 - Takeshi Suzuki, Keiichi Higeta, Yasuhiro Fujimura, Kazumasa Ando, Hiroaki Nambu, Ryo Yamagata, Atsuo Hotta, Kunihiko Yamaguchi:
Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functions. 163-174 - Bharadwaj S. Amrutur, Mark A. Horowitz:
Speed and power scaling of SRAM's. 175-185 - Christian C. Enz, Yuhua Cheng:
MOS transistor modeling for RF IC design. 186-201 - Bruno Stefanelli, Ian O'Connor, Laurent Quiquerez, Andreas Kaiser, Daniel Billet:
An analog beam-forming circuit for ultrasound imaging using switched-current delay lines. 202-211 - Un-Ku Moon:
CMOS high-frequency switched-capacitor filters for telecommunication applications. 212-220 - Ka Nang Leung, Philip K. T. Mok, Wing-Hung Ki, Johnny K. O. Sin:
Three-stage large capacitive load amplifier with damping-factor-control frequency compensation. 221-230 - Brian M. Ballweber, Ravi Gupta, David J. Allstot:
A fully integrated 0.5-5.5 GHz CMOS distributed amplifier. 231-239 - Piotr Dudek, Stanislaw Szczepanski, John V. Hatfield:
A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line. 240-247 - Wei-Shinn Wey, Yu-Chung Huang:
A CMOS delta-sigma true RMS converter. 248-257 - Koichi Murata, Taiichi Otsuji, Yuhki Imai, Suehiro Sugitani:
A distributed selector IC using GaAs MESFET's with multilayer-interconnection structure. 258-267 - Eduard Säckinger, Yusuke Ota, Thaddeus J. Gabara, Wilhelm C. Fischer:
A 15-mW, 155-Mb/s CMOS burst-mode laser driver with automatic power control and end-of-life detection. 269-275 - Shen-Iuan Liu, Chien-Hung Kuo, Ruey-Yuan Tsai, Jingshown Wu:
A double-sampling pseudo-two-path bandpass ΔΣ modulator. 276-280 - Ion E. Opris, Bill C. Wong, Sing W. Chin:
A pipeline A/D converter architecture with low DNL. 281-285 - HongMo Wang, Ali Hajimiri, Thomas H. Lee:
Comments on "Design issues in CMOS differential LC oscillators" [and reply]. 286-287
Volume 35, Number 3, March 2000
- Doug Garrity, Larry Starr:
Guest editorial. 294-296 - Eric Fogleman, Ian Galton, William Huff, Henrik Jensen:
A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR. 297-307 - Yun-Ti Wang, Behzad Razavi:
An 8-bit 150-MHz CMOS A/D converter. 308-317 - Iuri Mehr, Larry Singer:
A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC. 318-325 - Thomas H. Lee, Ali Hajimiri:
Oscillator phase noise: a tutorial. 326-336 - Alain-Serge Porret, Thierry Melly, Christian C. Enz, Eric A. Vittoz:
Design of high-Q varactors for low-power wireless applications using a standard CMOS process. 337-345 - Sunderarajan S. Mohan, Maria del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee:
Bandwidth extension in CMOS with optimized on-chip inductors. 346-355 - Francesco Svelto, Stefano Deantoni, Rinaldo Castello:
A 1.3 GHz low-phase noise fully tunable CMOS LC VCO. 356-361 - Srinath Sridharan, L. Richard Carley:
A 110 MHz 350 mW 0.6 μm CMOS 16-state generalized-target Viterbi detector for disk drive read channels. 362-370 - Michael S. Kappes:
A 3-V CMOS low-distortion class AB line driver suitable for HDSL applications. 371-376 - Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim:
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance. 377-384 - Abdellatif Bellaouar, Michael S. O'brecht, Amr M. Fahim, Mohamed I. Elmasry:
Low-power direct digital frequency synthesis for wireless communications. 385-390 - Ji-Ning Duan, Li-Jen Ko, Babak Daneshrad:
A highly versatile beamforming ASIC for application in broad-band fixed wireless access systems. 391-400 - Paul T. Capozza, Brian J. Holland, Thomas M. Hopkinson, Roberto L. Landrau:
A single-chip narrow-band frequency-domain excisor for a Global Positioning System (GPS) receiver. 401-411 - Bryan D. Ackland, A. Anesko, D. Brinthaupt, S. J. Daubert, Asawaree Kalavade, J. Knobloch, E. Micca, M. Moturi, Chris J. Nicol, Jay H. O'Neill, Joe Othmer, Eduard Sackinger, Kanwar Jit Singh, J. Sweet, C. J. Terman, Joseph Williams:
A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP. 412-424 - Steven Winegarden:
Bus architecture of a system on a chip with user-configurable system logic. 425-433 - Ilhami Torunoglu, Edoardo Charbon:
Watermarking-based copyright protection of sequential functions. 434-440 - Joop P. M. Van Lammeren, Roy W. B. Wissing:
Mixed-signal quadrature demodulator with a multicarrier regeneration system. 441-445 - Geoffrey B. Jackson, Saleel V. Awsare, Lawrence D. Engh, Peter Holzmann, Oliver C. Kao, Carl R. Palmer, Aditya Raina, Chun Mai-Liu, Albert V. Kordesch:
An analog record, playback, and processing system on a chip for mobile communications devices. 446-449 - Hee-Tae Ahn, David J. Allstot:
A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications. 450-454
Volume 35, Number 4, April 2000
- Prabir C. Maulik, Mandeep S. Chadha, Wai L. Lee, Philip J. Crawley:
A 16-bit 250-kHz delta-sigma modulator and decimation filter. 458-467 - Lucien J. Breems, Eric J. van der Zwan, Johan H. Huijsing:
A 1.8-mW CMOS ΣΔ modulator with integrated mixer for A/D conversion of IF signals. 468-475 - Farbod Behbahani, Weeguan Tan, Ali Karimi-Sanjaani, Andreas Roithmeier, Asad A. Abidi:
A broad-band tunable CMOS channel-select filter for a low-IF wireless receiver. 476-489 - Cicero S. Vaucher:
An adaptive PLL tuning system architecture combining high spectral purity and fast settling time. 490-502 - Shanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj:
Widely programmable high-frequency continuous-time filters in digital CMOS technology. 503-511 - Frank D. Bannon, John R. Clark, Clark T.-C. Nguyen:
High-Q HF microelectromechanical filters. 512-526 - Chien-Chang Liu, Carlos H. Mastrangelo:
A CMOS uncooled heat-balancing infrared imager. 527-535 - Takeshi Ikenaga, Takeshi Ogura:
A fully parallel 1-Mb CAM LSI for real-time pixel-parallel image processing. 536-544 - Ryu Ogiwara, Sumio Tanaka, Yasuo Itoh, Tadashi Miyakawa, Yoshiaki Takeuchi, Sumiko Mano Doumae, Hiroyuki Takenaka, Iwao Kunishima, Susumu Shuto, Osamu Hidaka, Sumito Ohtsuki, Shin'ichi Tanaka:
A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor. 545-551 - Oliver Weinfurtner, Daniel W. Storaska, Louis Hsu:
Advanced controlling scheme for a DRAM voltage generator system. 552-563 - Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kunihiko Yamaguchi, Noriyuki Homma, Atsuo Hotta:
Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz. 564-571 - Thomas Simon, Anantha P. Chandrakasan:
An ultra low power adaptive wavelet video encoder with integrated memory. 572-582 - Jinn-Shyan Wang, Po-Hui Yang, Duo Sheng:
Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops. 583-592 - Andre G. Metzger, Charles E. Chang, Ken D. Pedrotti, Steve M. Beccue, Keh-Chung Wang, Peter M. Asbeck:
A 10-Gb/s high-isolation, 16×16 crosspoint switch implemented with AlGaAs/GaAs HBT's. 593-600 - Ming-Dou Ker, Wen-Yu Lo:
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-μm silicide CMOS process. 601-611 - Suet Fong Tin, Ashraf A. Osman, Kartikeya Mayaram, Chenming Hu:
A simple subcircuit extension of the BSIM3v3 model for CMOS RF design. 612-624 - Ruchir Puri, Ching-Te Chuang:
Hysteresis effect in pass-transistor-based, partially depleted SOI CMOS circuits. 625-631 - Gianluca Giustolisi, Giuseppe Palmisano, T. Segreto:
1.2-V CMOS op-amp with a dynamically biased output stage. 632-636 - Fathi A. Farag, Carlos Galup-Montoro, Márcio C. Schneider:
Digitally programmable switched-current FIR filter for low-voltage applications. 637-641 - Siamak Mortezapour, Edward K. F. Lee:
A 1-V, 8-bit successive approximation ADC in standard CMOS process. 642-646 - Bang-Sup Song, Patrick L. Rakers, Steven F. Gillig:
A 1-V 6-b 50-MSamples/s current-interpolating CMOS ADC. 647-651 - Tadahiro Kuroda, Mototsugu Hamada:
Low-power CMOS digital design with dual embedded adaptive power supplies. 652-655 - Anders Berkeman, Viktor Öwall, Mats Torkelson:
A low logic depth complex multiplier using distributed arithmetic. 656-659 - Ahmad B. Dowlatabadi:
A robust, load-insensitive pad driver. 660-665
Volume 35, Number 5, May 2000
- Masao Taguchi, David B. Scott:
Guest editorial. 670-671 - Ken Takeuchi, Shinji Satoh, Ken-ichi Imamiya, Koji Sakui:
A source-line programming scheme for low-voltage operation NAND flash memories. 672-681 - Hiromi Nobukata, Shunsuke Takagi, Keizo Hiraga, Takeshi Ohgishi, Masaru Miyashita, Kazuto Kamimura, Shinji Hiramatsu, Kiyohisa Sakai, Takahiro Ishida, Hideki Arakawa, Masahiko Itoh, Ihachi Naiki, Masanori Noda:
A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming. 682-690 - Georg Braun, Heinz Hoenigschmid, Tobias Schlager, Werner Weber:
A robust 8F2 ferroelectric RAM cell with depletion device (DeFeRAM). 691-696 - Yeonbae Chung, Byung-Gil Jeon, Kang-Deog Suh:
A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme. 697-704 - Toshimasa Namekawa, Shinji Miyano, Ryo Fukuda, Ryo Haga, Osamu Wada, Hironori Banba, Satoru Takeda, Kazuhiro Suda, Kenichiro Mimoto, Satoshi Yamaguchi, Tsutomu Ohkubo, Hiroshi Takato, Kenji Numata:
Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus. 705-712 - Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman:
A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. 713-718 - Christl Lauterbach, Werner Weber, Dirk Romer:
Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps. 719-723 - Hiroki Morimura, Satoshi Shigematsu, Katsuyuki Machida:
A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors. 724-731 - Tarek Lulé, Michael Wagner, Marcus Verhoeven, Holger Keller, Markus Böhm:
100000-pixel, 120-dB imager in TFA technology. 732-739 - Thucydides Xanthopoulos, Anantha P. Chandrakasan:
A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization. 740-750 - Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara:
A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. 751-756 - Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee:
A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver. 757-764 - Hirad Samavati, Hamid R. Rategh, Thomas H. Lee:
A 5-GHz CMOS wireless LAN receiver front end. 765-772 - Wallace Ming Yip Wong, Ping Shing Hui, Zhiheng Chen, Keqiang Shen, Jack Lau, Philip C. H. Chan, Ping Keung Ko:
A wide tuning range gated varactor. 773-779 - Hamid R. Rategh, Hirad Samavati, Thomas H. Lee:
A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver. 780-787 - Christopher Lam, Behzad Razavi:
A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-μm CMOS technology. 788-794
Volume 35, Number 6, June 2000
- Angelo Nagari, Alessandro Mecchia, Ermes Viani, Sergio Pernici, Pierangelo Confalonieri, Germano Nicollini:
A 2.7-V 11.8-mW baseband ADC with 72-dB dynamic range for GSM applications. 798-806 - Kyoohyun Lim, Chan-Hong Park, Dal-Soo Kim, Beomsup Kim:
A low-noise phase-locked loop design by loop bandwidth optimization. 807-815 - Xiaodong Wang, Richard R. Spencer:
A CMOS two-path tree search detector. 816-825 - Yun-Nan Chang, Hiroshi Suzuki, Keshab K. Parhi:
A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder. 826-834 - Hugh Mair, Liming Xiu:
An architecture of high-performance frequency and phase synthesis. 835-846 - Hormoz Djahanshahi, C. André T. Salama:
Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications. 847-855 - Won Namgoong, Sydney Reader, Teresa H. Meng:
An all-digital low-power IF GPS synchronizer. 856-864 - Joonho Lim, Dong-Gyu Kim, Soo-Ik Chae:
nMOS reversible energy recovery logic for ultra-low-energy applications. 865-875 - Borivoje Nikolic, Vojin G. Oklobdzija, Vladimir Stojanovic, Wenyan Jia, James Kar-Shing Chiu, Michael Ming-Tak Leung:
Improved sense-amplifier-based flip-flop: design and measurements. 876-884 - Steven R. Carlough, Robert A. Philhower, Cliff A. Maier, Sam A. Steidl, Pete M. Campbell, Atul Garg, Kyung-Suc Nah, Matthew W. Ernest, James R. Loy, Thomas W. Krawczyk Jr., Peter F. Curran, Russell P. Kraft, Hans J. Greub, John F. McDonald:
A 2-GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip. 885-894 - Anil Samavedam, Aline Sadate, Kartikeya Mayaram, Terri S. Fiez:
A scalable substrate noise coupling model for design of mixed-signal IC's. 895-904 - Pietro Andreani, Sven Mattisson:
On the use of MOS varactors in RF VCOs. 905-910 - Indumini Ranmuthu, Paul M. Emerson, Ken Maggio, Hong Jiang, Ashish Manjekar, Bryan E. Bloodworth, Mark Guastaferro:
A design for high noise rejection in a pseudodifferential preamplifier for hard disk drives. 911-914 - Gijung Ahn, Deog-Kyoon Jeong, Gyudong Kim:
A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission. 915-918 - Ki-Hyuk Sung, Lee-Sup Kim:
Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler". 919-920 - Un-Ku Moon:
Correction to "CMOS high-frequency switched-capacitor filters for telecommunication applications". 920 - Brian M. Ballweber, Ravi Gupta, David J. Allstot:
Correction to "A fully integrated 0.5 - 5.5-GHz CMOS distributed amplifier". 921
Volume 35, Number 7, July 2000
- Stephen H. Lewis:
New associate editor [Editor]. 928 - Michael Schanz, Christian Nitta, Arndt Bußmann, Bedrich J. Hosticka, Reiner K. Wertheimer:
A high-dynamic-range CMOS image sensor for automotive applications. 932-938 - Stephan Benthien, Tarek Lulé, Bernd Schneider, Michael Wagner, Markus Verhoeven, Markus Böhm:
Vertically integrated sensors for advanced imaging applications. 939-945 - Willm Hinrichs, Jens Peter Wittenburg, Hanno Lieske, Helge Kloos, Martin Ohmacht, Peter Pirsch:
A 1.3-GOPS parallel DSP for high-performance image-processing applications. 946-952 - Cathleen Rooman, Daniël Coppée, Maarten Kuijk:
Asynchronous 250-Mb/s optical receivers with integrated detector in standard CMOS technology for optocoupler applications. 953-958 - Roberto Maurino, Peter Mole:
A 200-MHz IF 11-bit fourth-order bandpass ΔΣ ADC in SiGe. 959-967 - James C. Morizio, Michael Hoke, Taskin Koçak, Clark Geddie, Chris Hughes, John Perry, Srinadh Madhavapeddi, Michael H. Hood, George Lynch, Harufusa Kondoh, Toshio Kumamoto, Takashi Okuda, Hiroshi Noda, Masahiko Ishiwaki, Takahiro Miki, Masao Nakaya:
14-bit 2.2-MS/s sigma-delta ADC's. 968-976 - Armin Deiss, Dirk Pfaff, Qiuting Huang:
A 200-MHz sub-mA RF front end for wireless hearing aid applications. 977-986 - Bo Shi, Lars Sundström:
A 200-MHz IF BiCMOS signal component separator for linear LINC transmitters. 987-993 - Eric A. M. Klumperink, Sander L. J. Gierkink, Arnoud P. van der Wel, Bram Nauta:
Reducing MOSFET 1/f noise and power consumption by switched biasing. 994-1001 - Marc van Heijningen, John Compiet, Piet Wambacq, Stéphane Donnay, Marc Engels, Ivo Bolsens:
Analysis and experimental verification of digital substrate noise generation for epi-type substrates. 1002-1008 - James T. Kao, Anantha P. Chandrakasan:
Dual-threshold voltage techniques for low-power digital circuits. 1009-1018 - Nagendra Krishnapura, Peter R. Kinget:
A 5.3-GHz programmable divider for HiPerLAN in 0.25-μm CMOS. 1019-1024 - Nobuhiro Ide, Masashi Hirano, Yukio Endo, Shin-ichi Yoshioka, Hiroaki Murakami, Atsushi Kunimatsu, Toshinori Sato, Takayuki Kamei, Toyoshi Okada, Masakazu Suzuoki:
2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing. 1025-1033 - Bram De Muer, Marc Borremans, Michiel Steyaert, G. Li Puma:
A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization. 1034-1038 - Cicero S. Vaucher, Igor Ferencic, Matthias Locher, Sebastian Sedvallson, Urs Voegeli, Zhenhua Wang:
A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology. 1039-1045 - Robert St. Pierre:
Low-power BiCMOS op-amp with integrated current-mode charge pump. 1046-1050 - Gerd Schuppener, Costantino Pala, Mehran Mokhtari:
Investigation on low-voltage low-power silicon bipolar design topology for high-speed digital circuits. 1051-1054 - Yang Ni, Jianhong Guan:
A 256×256 pixel smart CMOS image sensor for line-based stereo vision applications. 1055-1061
Volume 35, Number 8, August 2000
- Ichiro Fujimori, Akihiko Nogi, Tetsuro Sugimoto:
A multibit delta-sigma audio DAC with 120-dB dynamic range. 1066-1073 - Russell E. Radke, Aria Eshraghi, Terri S. Fiez:
A 14-bit current-mode ΣΔ DAC based upon rotated data weighted averaging. 1074-1084 - Hooman Darabi, Asad A. Abidi:
A 4.5-mW 900-MHz CMOS receiver for wireless paging. 1085-1096 - Hans Voorman, Hugo Veenstra:
Tunable high-frequency Gm-C filters. 1097-1108 - Kazuya Yamamoto, Satoshi Suzuki, Kazutomi Mori, Tomoyuki Asada, Toshio Okuda, Akira Inoue, Takeshi Miura, Kenichiro Chomei, Ryo Hattori, Masahide Yamanouchi, Teruyuki Shimura:
A 3.2-V operation single-chip dual-band AlGaAs/GaAs HBT MMIC power amplifier with active feedback circuit technique. 1109-1120 - Shihab Al-Kuran, Norman Scheinberg, John van Saders:
GaAs switched capacitor DC-to-DC converter. 1121-1127 - Guang-Kaai Dehng, June-Ming Hsu, Ching-Yuan Yang, Shen-Iuan Liu:
Clock-deskew buffer using a SAR-controlled delay-locked loop. 1128-1136 - Joonsuk Lee, Beomsup Kim:
A low-noise fast-lock phase-locked loop with adaptive bandwidth control. 1137-1145 - Spyros Kavadias, Bart Dierickx, Danny Scheffer, Andre Alaerts, Dirk Uwaerts, Jan Bogaerts:
A logarithmic response CMOS image sensor with on-chip calibration. 1146-1152 - Takashi Okuda, Isao Naritake, Tadahiko Sugibayashi, Yuji Nakajima, Tatsunori Murotani:
A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor. 1153-1158 - Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Kunihiko Yamaguchi, Atsuo Hotta, Noriyuki Homma:
A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM. 1159-1168 - Tadaaki Yamauchi, Fukashi Morishita, Shigenobu Maeda, Kazutami Arimoto, Kazuyasu Fujishima, Hideyuki Ozaki, Tsutomu Yoshihara:
High-performance embedded SOI DRAM architecture for the low-power supply. 1169-1178 - Takashi Kono, Takeshi Hamamoto, Katsuyoshi Mitsui, Yasuhiro Konishi, Tsutomu Yoshihara, Hideyuki Ozaki:
A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs. 1179-1185 - Keith A. Bowman, Xinghai Tang, John C. Eble, James D. Menldl:
Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance. 1186-1193 - Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Wu, Hun-Hsien Chang:
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications. 1194-1199 - Simon J. Lovett, Gary A. Gibbs, Ashish Pancholy:
Yield and matching implications for static RAM memory array sense-amplifier design. 1200-1204 - Robert Bogdan Staszewski, Khurram Muhammad, Poras T. Balsara:
A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels. 1205-1210 - Guang-Kaai Dehng, Ching-Yuan Yang, June-Ming Hsu, Shen-Iuan Liu:
A 900-MHz 1-V CMOS frequency synthesizer. 1211-1214 - Andrea Baschirotto, F. Severi, Rinaldo Castello:
A 200-Ms/s 10-mW switched-capacitor filter in 0.5-μm CMOS technology. 1215-1219 - José M. de la Rosa, Belén Pérez-Verdú, Rocío del Río, Ángel Rodríguez-Vázquez:
A CMOS 0.8-μm transistor-only 1.63-MHz switched-current bandpass ΣΔ modulator for AM signal A/D conversion. 1220-1226 - Jongshin Shin, In-Young Chung, Young June Park, Hong-Shick Min:
A new charge pump without degradation in threshold voltage due to body effect [memory applications]. 1227-1230 - Aleksander Dec, Ken Suyama:
A 1.9-GHz CMOS VCO with micromachined electromechanically tunable capacitors. 1231-1237 - Johan van der Tang, Dieter Kasperkovitz:
A low-phase-noise reference oscillator with integrated pMOS varactors for digital satellite receivers. 1238-1243 - Keng Leong Fong:
High-frequency analysis of linearity improvement technique of common-emitter transconductance stage using a low-frequency-trap network. 1249-1252 - Albert G. Baca, Edwin J. Heller, Stephen A. Casalnuovo, Greg C. Frye-Mason, John F. Klem, T. J. Drummond:
Addition to "Development of a GaAs monolithic surface acoustic wave integrated circuit". 1253 - Albert G. Baca, Edwin J. Heller, Stephen A. Casalnuovo, Greg C. Frye-Mason, John F. Klem, T. J. Drummond:
Addition to "Development of a GaAs monolithic surface acoustic wave integrated circuit". 1253
Volume 35, Number 9, September 2000
- Jens Müllrich, Herbert Thurner, Ernst Müllner, Joseph F. Jensen, William E. Stanchina, Michael Kardos, Hans-Martin Rein:
High-gain transimpedance amplifier in InP-based HBT technology for the receiver in 40-Gb/s optical-fiber TDM links. 1260-1265 - Michael G. Chen, Johannes K. Notthoff:
A 3.3-V 21-Gb/s PRBS generator in AlGaAs/GaAs HBT technology. 1266-1270 - Anthony Jayakumar, Melody S. Bustos, David Cheskis, Stephen J. Pietrucha, Mark Bonelli, Shihab Al-Kuran, Norman Scheinberg:
3-V MSM-TIA for Gigabit Ethernet. 1271-1275 - Elizabeth C. Glass, Jenn-Hwa Huang, Joseph Staudinger, Michael Shields, Marino John Martinez, Olin L. Martin, Wendy Valentine, Ellen Lan:
Application of enhancement mode FET technology for wireless subscriber transmit/receive circuits. 1276-1284 - Karthikeyan Krishnamurthy, Ramakrishna Vetury, Stacia Keller, Umesh K. Mishra, Mark J. W. Rodwell, Stephen I. Long:
Broadband GaAs MESFET and GaN HEMT resistive feedback power amplifiers. 1285-1292 - Kohji Matsunaga, Ikuo Miura, Naotaka Iwata:
A CW 4-W Ka-band power amplifier utilizing MMIC multichip technology. 1293-1297 - O. S. Andy Tang, S. M. Joseph Liu, Pane C. Chao, Wendel M. T. Kong, K. C. Hwang, Kirby Nichols, John Heaton:
Design and fabrication of a wideband 56- to 63-GHz monolithic power amplifier with very high power-added efficiency. 1298-1306 - Colin S. Whelan, Phil F. Marsh, William E. Hoke, Rebecca A. McTaggart, Peter S. Lyman, Peter J. Lemonias, Steven M. Lardizabal, Robert E. Leoni III, Steven J. Lichwala, Thomas E. Kazior:
Millimeter-wave low-noise and high-power metamorphic HEMT amplifiers and devices on GaAs substrates. 1307-1311 - Steffen Kudszus, William H. Haydl, Markus Neumann, Michael Schlechtweg:
94/47-GHz regenerative frequency divider MMIC with low conversion loss. 1312-1317 - John R. Long:
A low-voltage 5.1-5.8-GHz image-reject downconverter RF IC. 1320-1328 - Liwei Sheng, Jonathan C. Jensen, Lawrence E. Larson:
A wide-bandwidth Si/SiGe HBT direct conversion sub-harmonic mixer/downconverter. 1329-1337 - Pei-Der Tseng, Liyang Zhang, Guang-Bo Gao, M. Frank Chang:
A 3-V monolithic SiGe HBT power amplifier for dual-mode (CDMA/AMPS) cellular handset applications. 1338-1344 - Günter Grau, Ulrich Langmann, Wolfgang Winkler, Dieter Knoll, Jörg Osten, Klaus Pressel:
A current-folded up-conversion mixer and VCO with center-tapped inductor in a SiGe-HBT technology for 5-GHz wireless LAN applications. 1345-1352 - Yuriy M. Greshishchev, Peter Schvan:
SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application. 1353-1359 - John W. M. Rogers, José Macedo, Calvin Plett:
The effect of varactor nonlinearity on the phase noise of completely integrated VCOs. 1360-1367 - John R. Long:
Monolithic transformers for silicon RF IC design. 1368-1382
Volume 35, Number 10, October 2000
- Dietmar Gogl, Horst-Lothar Fiedler, Markus Spitz, Bernard Parmentier:
A 1-Kbit EEPROM in SIMOX technology for high-temperature applications up to 250°C. 1387-1395 - Nobutaro Shibata, Hiroki Morimura, Mitsuru Harada:
1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs. 1396-1407 - Jae-Kyung Wee, Woodward Yang, Eui-Kyu Ryou, Joe-Sun Choi, Seung-Han Ahn, Jin-Yong Chung, Sea-Chung Kim:
An antifuse EPROM circuitry scheme for field-programmable repair in DRAM. 1408-1414 - Toru Tanzawa, Yoshinori Takano, Tadayuki Taura, Shigeru Atsumi:
Design of a sense circuit for low-voltage flash memories. 1415-1421 - Peter Hazucha, Christer Svensson, Stephen A. Wender:
Cosmic-ray soft error rate characterization of a standard 0.6-μm CMOS process. 1422-1429 - Jae Joon Kim, Sang-Bo Lee, Tae-Sung Jung, Chang-Hyun Kim, Soo-In Cho, Beomsup Kim:
A low-jitter mixed-mode DLL for high-speed DRAM applications. 1430-1436 - William B. Wilson, Un-Ku Moon, Kadaba R. Lakshmikumar, Liang Dai:
A CMOS self-calibrating frequency synthesizer. 1437-1444 - Ching-Yuan Yang, Shen-Iuan Liu:
Fast-switching frequency synthesizer with a discriminator-aided phase detector. 1445-1452 - Woogeun Rhee, Bang-Sup Song, Akbar Ali:
A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator. 1453-1460 - Manolis Terrovitis, Robert G. Meyer:
Intermodulation distortion in current-commutating CMOS mixers. 1461-1473 - Po-Chiun Huang, Yi-Huei Chen, Chorng-Kuang Wang:
A 2-V 10.7-MHz CMOS limiting amplifier/RSSI. 1474-1480 - Yue Tan, Mahender Kumar, Johnny K. O. Sin, Longxing Shi, Jack Lau:
A 900-MHz fully integrated SOI power amplifier for single-chip wireless transceiver applications. 1481-1486 - Wentai Liu, Kasin Vichienchom, Mark Clements, Stephen C. DeMarco, Chris Hughes, Elliot McGucken, Mark S. Humayun, Eugene de Juan Jr, James D. Weiland, Robert J. Greenberg:
A neuro-stimulus chip with telemetry unit for retinal prosthetic device. 1487-1497 - Hiroshi Kawaguchi, Koichi Nose, Takayasu Sakurai:
A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current. 1498-1501 - Ralf Achenbach, Martin Feuerstack-Raible, Friedrich Hiller, Michael Keller, Karlheinz Meier, Harald Rudolph, Roland Saur-Brosch:
A digitally temperature-compensated crystal oscillator. 1502-1506 - Elvi Räisänen-Ruotsalainen, Timo Rahkonen, Juha Kostamovaara:
An integrated time-to-digital converter with 30-ps single-shot precision. 1507-1510 - Jinn-Shyan Wang, Chung-Hsun Huang:
High-speed and low-power CMOS priority encoders. 1511-1514 - James D. Meindl, Jeffrey A. Davis:
The fundamental limit on binary switching energy for terascale integration (TSI). 1515-1516 - Gustavo A. Ruiz:
Addition to "Evaluation of three 32-bit CMOS" adders in DCVS logic for self-timed circuits". 1517 - Frank D. Bannon, John R. Clark, Clark T.-C. Nguyen:
Correction to "high-Q Hf microelectromechanical filters". 1517
Volume 35, Number 11, November 2000
- Raymond A. Heald, Kathirgamar Aingaran, Chaim Amir, Michael Ang, Michael Boland, Pankaj Dixit, Gary Gouldsberry, Dale Greenley, Joel Grinberg, Jason M. Hart, Tim Horel, Wen-Jay Hsu, James M. Kaku, Chin Kim, Song Kim, Fabian Klass, Hang Kwan, Gary Lauterbach, Roger Lo, Hugh McIntyre, Anup Mehta, David Murata, Sophie Nguyen, Yet-Ping Pai, Subeer Patel, Ken Shin, Kenway Tam, Sai Vishwanthaiah, John Wu, Gin Yee, Eileen You:
A third-generation SPARC V9 64-b microprocessor. 1526-1538 - Stefan Rusu, Gadi Singer:
The first IA-64 microprocessor. 1539-1544 - Simon Tam, Stefan Rusu, Utpal Nagarji Desai, Robert Kim, Ji Zhang, Ian Young:
Clock generation and distribution for the first IA-64 microprocessor. 1545-1552 - Vadim Gutnik, Anantha P. Chandrakasan:
Active GHz clock network using distributed PLLs. 1553-1560 - William C. Athas, Nestoras Tzartzanis, Weihua Mao, Lena Peterson, Rajat Lal, Kisup Chong, Joong-Seok Moon, Lars J. Svensson, Michael Bolotski:
The design and implementation of a low-power clock-powered microprocessor. 1561-1570 - Thomas D. Burd, Trevor Pering, Anthony J. Stratakos, Robert W. Brodersen:
A dynamic voltage scaled microprocessor system. 1571-1580 - Takanori Saeki, Masafumi Mitsuishi, Hiroaki Iwaki, Mitsuaki Tagishi:
A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand". 1581-1590 - Ming-Ju Edward Lee, William J. Dally, Patrick Chiang:
Low-power area-efficient high-speed I/O circuit techniques. 1591-1599 - Gu-Yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos, Mark A. Horowitz:
A variable-frequency parallel I/O interface with adaptive power-supply regulation. 1600-1610 - Muneo Fukaishi, Kazuyuki Nakamura, Hideki Heiuchi, Yoshinori Hirota, Yoetsu Nakazawa, Hidenori Ikeno, Hiroshi Hayama, Michio Yotsuyanagi:
A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays. 1611-1618 - Evelina Yeung, Mark A. Horowitz:
A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation. 1619-1628 - Koichi Takeda, Yoshiharu Aimoto, Noritsugu Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Kenji Noda, Koujirou Matsui, Shinya Itoh, Sadaaki Masuoka, Tadahiko Horiuchi, Atsushi Nakagawa, Kenju Shimogawa, Hiroyuki Takahashi:
A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. 1631-1640 - Harold Pilo, Archie Allen, Jim Covino, Patrick Hansen, Steve Lamphier, Chris Murphy, Terry Traver, Pui Yee:
An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin. 1641-1647 - Shigeru Atsumi, Akira Umezawa, Tooru Tanzawa, Tadayuki Taura, Hitoshi Shiga, Yoshinori Takano, Takeshi Miyaba, Michiharu Matsui, Hiroshi Watanabe, Kazuaki Isobe, Shota Kitamura, Seiji Yamada, Masanobu Saito, Seiichi Mori, Toshiharu Watanabe:
A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme. 1648-1654 - Giovanni Campardo, Rino Micheloni, Stefano Commodaro, Emilio Yero, Matteo Zammattio, Sabina Mognoni, Andrea Sacco, Massimiliano Picca, Alessandro Manstretta, Marco Scotti, Ilaria Motta, C. Golla, Andrea Pierin, Roberto Bez, Alessandro Grossi, Alberto Modelli, Angelo Visconti, Osama Khouri, Guido Torelli:
40-mm2 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory. 1655-1667 - Yasuhiro Agata, Kenji Motomochi, Yoshifumi Fukushima, Masanori Shirahama, Marefusa Kurumada, Naoki Kuroda, Hiroyuki Sadakata, Kohtaro Hayashi, Toshio Yamada, Kazunari Takahashi, Tsutomu Fujita:
An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D2/RAM). 1668-1672 - Osamu Takahashi, Sang H. Dhong, Manabu Ohkubo, Shohji Onishi, Robert H. Dennard, Robert Hannon, Scott Crowder, Subramanian S. Iyer, Matthew R. Wordeman, Bijan Davari, William B. Weinberger, Naoaki Aoki:
1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro. 1673-1679 - Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara:
A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. 1680-1689 - Byung-Gil Jeon, Mun-Kyu Choi, Yoonjong Song, Seung-Kyu Oh, Yeonbae Chung, Kang-Deog Suh, Kinam Kim:
A 0.4-μm 3.3-V 1T1C 4-Mb nonvolatile ferroelectric RAM with fixed bitline reference voltage scheme and data protection circuit. 1690-1694 - Hui Zhang, Vandana Prabhu, George Varghese, Marlene Wan, Martin Benes, Arthur Abnous, Jan M. Rabaey:
A 1-V heterogeneous reconfigurable DSP IC for wireless baseband digital signal processing. 1697-1704 - Philippe Mosch, Gerard van Oerle, Stefan Menzl, Nicolas Rougnon-Glasson, Koen Van Nieuwenhove, Mark Wezelenburg:
A 660-μW 50-Mops 1-V DSP for a hearing aid chip set. 1705-1712 - Masafumi Takahashi, Tsuyoshi Nishikawa, Mototsugu Hamada, Toshinari Takayanagi, Hideho Arakida, Noriaki Machida, Hideaki Yamamoto, Toshihide Fujiyoshi, Yoko Ohashi, Osamu Yamagishi, Tatsuo Samata, Atsushi Asano, Toshihiro Terazawa, Kenji Ohmori, Yoshinori Watanabe, Hiroki Nakamura, Shigenobu Minami, Tadahiro Kuroda, Tohru Furuyama:
A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM. 1713-1721 - Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Gert-Jan van Rootselaar:
Heterogeneous multiprocessor for the management of real-time video and graphics streams. 1722-1731 - Daniel Doswald, Jürg Häfliger, Patrick Blessing, Norbert Felber, Peter Niederer, Wolfgang Fichtner:
A 30-frames/s megapixel real-time CMOS image processor. 1732-1743 - Toshiyuki Nozawa, Masahiro Konda, Masanori Fujibayashi, Makoto Imai, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi:
A parallel vector-quantization processor eliminating redundant calculations for real-time motion picture compression. 1744-1750
Volume 35, Number 12, December 2000
- Krishnaswamy Nagaraj, David A. Martin, Mark A. Wolfe, Ranjan Chattopadhyay, Shanthi Pavan, Jason Cancio, T. R. Viswanathan:
A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process. 1760-1768 - Hui Pan, Masahiro Segami, Michael Choi, Jing Cao, Asad A. Abidi:
A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over 80-dB SFDR. 1769-1780 - Myung-Jun Choe, Bang-Sup Song, Kantilal Bacrania:
A 13-b 40-MSamples/s CMOS pipelined folding ADC with background offset trimming. 1781-1790 - Carl Moreland, Frank Murden, Michael Elliott, Joe Young, Mike Hensley, Russell Stop:
A 14-bit 100-Msample/s subranging ADC. 1791-1798 - Ali Tabatabaei, Bruce A. Wooley:
A two-path bandpass sigma-delta modulator with extended noise shaping. 1799-1809 - Eric J. van der Zwan, Kathleen Philips, Corné A. A. Bastiaansen:
A 10.7-MHz IF-to-baseband ΣΔ A/D conversion system for AM/FM radio receivers. 1810-1819 - Ichiro Fujimori, Lorenzo Longo, Armond Hairapetian, Kazushi Seiyama, Steve Kosic, Jun Cao, Shu-Lap Chan:
A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8× oversampling ratio. 1820-1828 - Yves Geerts, Michel S. J. Steyaert, Willy Sansen:
A high-performance multibit ΔΣ CMOS ADC. 1829-1840 - Alex R. Bugeja, Bang-Sup Song:
A self-trimming 14-b 100-MS/s CMOS DAC. 1841-1852 - Mourad N. El-Gamal, Rola A. Baki, Amir Bar-Dor:
30-100-MHz NPN-only variable-gain class-AB instantaneous companding filters for 1.2-V applications. 1853-1864 - Patrick J. Quinn, Koen van Hartingsveldt, Arthur H. M. van Roermund:
A 10.7-MHz CMOS SC radio IF filter using orthogonal hardware modulation. 1865-1876 - Anton Bakker, Kevin Thiele, Johan H. Huijsing:
A CMOS nested-chopper instrumentation amplifier with 100-nV offset. 1877-1883 - Eduard Säckinger, Wilhelm C. Fischer:
A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers. 1884-1888 - Rajeevan Mahadevan, David A. Johns:
A differential 160-MHz self-terminating adaptive CMOS line driver. 1889-1894 - Michel S. J. Steyaert, Johan Janssens, Bram De Muer, Marc Borremans, Nobuyuki Itoh:
A 2-V CMOS cellular transceiver front-end. 1895-1907 - Farbod Behbahani, John C. Leete, Yoji Kishigami, Andreas Roithmeier, Koichi Hoshino, Asad A. Abidi:
A 2.4-GHz low-IF receiver for wideband WLAN in 6-μm CMOS-architecture and front-end. 1908-1916 - James P. Maligeorgos, John R. Long:
A low-voltage 5.1-5.8-GHz image-reject receiver with wide dynamic range. 1917-1926 - Ting-Ping Liu, Eric Westerwick:
5-GHz CMOS radio transceiver front-end chipset. 1927-1933 - Edwin E. Bautista, Babak Bastani, Joseph Heck:
A high IIP2 downconversion mixer using dynamic matching. 1934-1941 - Shoji Otaka, Gaku Takemura, Hiroshi Tanimoto:
A low-power low-noise accurate linear-in-dB variable-gain amplifier with 500-MHz bandwidth. 1942-1948 - Yuriy M. Greshishchev, Peter Schvan, Jonathan L. Showell, Mu-Liang Xu, Jugnu J. Ojha, Jonathan E. Rogers:
A fully integrated SiGe receiver IC for 10-Gb/s data rate. 1949-1957 - Tobias Ellermeyer, Ulrich Langmann, Berthold Wedding, Wolfgang Pöhlmann:
A 10-Gb/s eye-opening monitor IC for decision-guided adaptation of the frequency response of an optical receiver. 1958-1963 - Amit Gattani, David W. Cline, Paul J. Hurst, Paul M. Mosinskis:
A CMOS HDSL2 analog front-end. 1964-1975 - Bernhard Zojer, Rüdiger Koban, Joachim Pichler, Gerhard Paoli:
A broadband high-voltage SLIC for a splitter- and transformerless combined ADSL-Lite/POTS linecard. 1976-1987 - Kenji Kawai, Haruhiko Ichino:
A 0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSI. 1988-1991 - Mounir Meghelli, Benjamin D. Parker, Herschel A. Ainspan, Mehmet Soyuer:
SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems. 1992-1995 - George Chien, Paul R. Gray:
A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications. 1996-1999 - Mitsuru Harada, Tsuneo Tsukahara, Junichi Kodate, Akihiro Yamagishi, Junzo Yamada:
2-GHz RF front-end circuits in CMOS/SIMOX operating at an extremely low voltage of 0.5 V. 2000-2004 - Christoph Kuratli, Qiuting Huang:
A CMOS ultrasound range-finder microsystem. 2005-2017 - Walter Snoeys, Giovanni Anelli, Michael Campbell, Eugenio Cantatore, Federico Faccio, Erik H. M. Heijne, Senior Pierre Jarron, Kostas Kloukinas, Alessandro Marchioro, Paulo Moreira, Thomas Toifl, Kenneth Wyllie:
Integrated circuits for particle physics experiments. 2018-2030 - Iliana L. Fujimori, Ching-Chun Wang, Charles G. Sodini:
A 256×256 CMOS differential passive pixel imager with FPN reduction techniques. 2031-2037 - Kazuya Yonemoto, Hirofumi Sumi:
A CMOS image sensor with a simple fixed-pattern-noise-reduction technology and a hole accumulation diode. 2038-2043 - Tetsuo Yamada, Katsumi Ikeda, Yong-Gwan Kim, Hideki Wakoh, Tetsuo Toma, Tomohiro Sakamoto, Kazuaki Ogawa, Eiichi Okamoto, Kazuyuki Masukane, Kazuya Oda, Masafumi Inuiya:
A progressive scan CCD image sensor for DSC applications. 2044-2054
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