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Gin Yee
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2000 – 2009
- 2002
- [j4]Gregg N. Hoyer, Gin Yee, Carl Sechen:
Locally clocked pipelines and dynamic logic. IEEE Trans. Very Large Scale Integr. Syst. 10(1): 58-62 (2002) - 2000
- [j3]Raymond A. Heald, Kathirgamar Aingaran, Chaim Amir, Michael Ang, Michael Boland, Pankaj Dixit, Gary Gouldsberry, Dale Greenley, Joel Grinberg, Jason M. Hart, Tim Horel, Wen-Jay Hsu, James M. Kaku, Chin Kim, Song Kim, Fabian Klass, Hang Kwan, Gary Lauterbach, Roger Lo, Hugh McIntyre, Anup Mehta, David Murata, Sophie Nguyen, Yet-Ping Pai, Subeer Patel, Ken Shin, Kenway Tam, Sai Vishwanthaiah, John Wu, Gin Yee, Eileen You:
A third-generation SPARC V9 64-b microprocessor. IEEE J. Solid State Circuits 35(11): 1526-1538 (2000) - [j2]Gin Yee, Carl Sechen:
Clock-delayed domino for dynamic circuit design. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 425-430 (2000) - [c6]Jovanka Ciric, Gin Yee, Carl Sechen:
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. DATE 2000: 277-282 - [c5]Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen:
Output Prediction Logic: A High-Performance CMOS Design Technique. ICCD 2000: 247-254 - [c4]Gin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen:
An Automated Shielding Algorithm and Tool For Dynamic Circuits. ISQED 2000: 369-374
1990 – 1999
- 1999
- [j1]Fabian Klass, Chaim Amir, Ashutosh Das, Kathirgamar Aingaran, Cindy Truong, Richard Wang, Anup Mehta, Raymond A. Heald, Gin Yee:
A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors. IEEE J. Solid State Circuits 34(5): 712-716 (1999) - [c3]Tyler Thorp, Gin Yee, Carl Sechen:
Design and Synthesis of Monotonic Circuits. ICCD 1999: 569-572 - 1998
- [c2]Tyler Thorp, Gin Yee, Carl Sechen:
Domino logic synthesis using complex static gates. ICCAD 1998: 242-247 - 1996
- [c1]Gin Yee, Carl Sechen:
Clock-Delayed Domino for Adder and Combinational Logic Desig. ICCD 1996: 332-337
Coauthor Index
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