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"An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM ..."

Yasuhiro Agata et al. (2000)

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DOI: 10.1109/4.881213

access: closed

type: Journal Article

metadata version: 2022-04-13

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  - https://dblp.org/rec/journals/jssc/AgataMFSKKSHYTF00
Yasuhiro Agata, Kenji Motomochi, Yoshifumi Fukushima, Masanori Shirahama, Marefusa Kurumada, Naoki Kuroda, Hiroyuki Sadakata, Kohtaro Hayashi, Toshio Yamada, Kazunari Takahashi, Tsutomu Fujita:
An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D²/RAM). IEEE J. Solid State Circuits 35(11): 1668-1672 (2000)

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